Patents by Inventor Remi Brechignac

Remi Brechignac has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11502227
    Abstract: An electronic device includes a first electronic component and a second electronic. Each electronic component includes a carrier substrate having a back side and a front side, an electronic chip including an integrated optical element, an overmolded transparent block encapsulating the electronic chip above the carrier substrate, and electrical connections between the electronic chip and electrical contacts of the carrier substrate. An overmolded grid encapsulates and holds the first and second electronic components. The grid is configured so that sides of the first and second electronic components are at least partially exposed.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: November 15, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
  • Publication number: 20220310869
    Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 29, 2022
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Remi BRECHIGNAC, Jean-Michel RIVIERE
  • Patent number: 11387381
    Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: July 12, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
  • Patent number: 11380663
    Abstract: An opaque dielectric carrier and confinement substrate is formed by a stack of layers laminated on each other. The stack includes a solid back layer and a front frame having a peripheral wall and an intermediate partition which delimits two cavities located on top of the solid back layer and on either side of the intermediate partition. Electronic integrated circuit (IC) chips are located inside the cavities and mounted on top of the solid back layer. Each IC chip includes an integrated optical element. Electrical connections are provided between the IC chips and back electrical contacts of the solid back layer. Transparent encapsulation blocks are molded in the cavities to embed the IC chips.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: July 5, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
  • Patent number: 11322666
    Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated within a first encapsulation layer, and the receiver is encapsulated within a second encapsulation layer. An opaque layer covers the first encapsulation layer (encapsulating the receiver) and covers the second encapsulation layer (encapsulating the emitter). The first and second encapsulation layers are separated by a region of opaque material. This opaque material may be provided by the opaque layer or an opaque fill.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: May 3, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
  • Publication number: 20220102591
    Abstract: The present description concerns a package for an electronic device. The package including a plate and a lateral wall, separated by a layer made of a bonding material and at least one region made of a material configured to form in the region an opening between the inside and the outside of the package when the package is heated.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 31, 2022
    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Olivier ZANELLATO, Remi BRECHIGNAC, Jerome LOPEZ
  • Publication number: 20210135038
    Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip.
    Type: Application
    Filed: October 15, 2020
    Publication date: May 6, 2021
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Remi BRECHIGNAC, Jean-Michel RIVIERE
  • Publication number: 20210135069
    Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated within a first encapsulation layer, and the receiver is encapsulated within a second encapsulation layer. An opaque layer covers the first encapsulation layer (encapsulating the receiver) and covers the second encapsulation layer (encapsulating the emitter). The first and second encapsulation layers are separated by a region of opaque material. This opaque material may be provided by the opaque layer or an opaque fill.
    Type: Application
    Filed: October 15, 2020
    Publication date: May 6, 2021
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Remi BRECHIGNAC, Jean-Michel RIVIERE
  • Publication number: 20210066554
    Abstract: An electronic device includes a first electronic component and a second electronic. Each electronic component includes a carrier substrate having a back side and a front side, an electronic chip including an integrated optical element, an overmolded transparent block encapsulating the electronic chip above the carrier substrate, and electrical connections between the electronic chip and electrical contacts of the carrier substrate. An overmolded grid encapsulates and holds the first and second electronic components. The grid is configured so that sides of the first and second electronic components are at least partially exposed.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 4, 2021
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Remi BRECHIGNAC, Jean-Michel RIVIERE
  • Publication number: 20210066271
    Abstract: An opaque dielectric carrier and confinement substrate is formed by a stack of layers laminated on each other. The stack includes a solid back layer and a front frame having a peripheral wall and an intermediate partition which delimits two cavities located on top of the solid back layer and on either side of the intermediate partition. Electronic integrated circuit (IC) chips are located inside the cavities and mounted on top of the solid back layer. Each IC chip includes an integrated optical element. Electrical connections are provided between the IC chips and back electrical contacts of the solid back layer. Transparent encapsulation blocks are molded in the cavities to embed the IC chips.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 4, 2021
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Remi BRECHIGNAC, Jean-Michel RIVIERE
  • Patent number: 9196590
    Abstract: An electronic package includes an integrated circuit chip mounted to a support plate and encapsulated by an encapsulating body. The package includes at least one weakening deep perforation. The perforation is formed in either the support plate or the encapsulating body, and functions to reduce a resistance of the package to bending stresses perpendicular to the support plate.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: November 24, 2015
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Francis Steffen, Delphine Mathey, Gilbert Assaud, Rémi Brechignac
  • Publication number: 20150262941
    Abstract: An electronic package includes an integrated circuit chip mounted to a support plate and encapsulated by an encapsulating body. The package includes at least one weakening deep perforation. The perforation is formed in either the support plate or the encapsulating body, and functions to reduce a resistance of the package to bending stresses perpendicular to the support plate.
    Type: Application
    Filed: March 6, 2015
    Publication date: September 17, 2015
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Francis Steffen, Delphine Mathey, Gilbert Assaud, Rémi Brechignac
  • Patent number: 9136292
    Abstract: An electronic package includes a substrate wafer having front and rear faces. An emitting integrated circuit chip is mounted to the front face of the substrate wafer and includes a light radiation optical emitter. A receiving integrated circuit chip is also mounted to the front face of the substrate wafer and includes at least one light radiation optical sensor. A transparent encapsulant extends above the optical sensor and the optical emitter. An opaque encapsulant encapsulates the transparent encapsulant. The opaque encapsulant has a front window situated above the optical emitter and which is offset laterally relative to the optical sensor. The transparent encapsulant accordingly has an uncovered front face situated above the optical emitter and offset laterally relative to the optical sensor. The opaque encapsulant may include an additional front window. The receiving integrated circuit chip further includes a second optical sensor situated opposite the additional front window.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: September 15, 2015
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac
  • Patent number: 9076749
    Abstract: An electronic system includes a first integrated-circuit chip and a second integrated-circuit chip. A first substrate wafer is positioned between the first and second integrated-circuit chips and configured with a first connection network to make electrical connection to the first integrated-circuit chip. A second substrate wafer, configured with a second connection network to make electrical connection to the second integrated-circuit chip, is positioned facing the first substrate wafer. The connection networks of the first and second substrate wafers are electrically connected through connection structures. A third substrate wafer, including a third connection network, is thermally in contact with the first integrated-circuit chip and electrically connected to the first connection network of the first substrate wafer through further connection structures. The further connection structure may be formed using another substrate wafer.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: July 7, 2015
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Rémi Brechignac
  • Publication number: 20150102500
    Abstract: An electronic system includes a first integrated-circuit chip and a second integrated-circuit chip. A first substrate wafer is positioned between the first and second integrated-circuit chips and configured with a first connection network to make electrical connection to the first integrated-circuit chip. A second substrate wafer, configured with a second connection network to make electrical connection to the second integrated-circuit chip, is positioned facing the first substrate wafer. The connection networks of the first and second substrate wafers are electrically connected through connection structures. A third substrate wafer, including a third connection network, is thermally in contact with the first integrated-circuit chip and electrically connected to the first connection network of the first substrate wafer through further connection structures. The further connection structure may be formed using another substrate wafer.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 16, 2015
    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Romain Coffy, Rémi Brechignac
  • Patent number: 9006904
    Abstract: An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: April 14, 2015
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Dominique Marais, Jacques Chavade, Rémi Brechignac, Eric Saugier, Romain Coffy, Luc Petit
  • Patent number: 8482116
    Abstract: A semiconductor device includes at least one first component (5) (for example, a first integrated circuit), having a front face provided with electrical connection pads. The first component is embedded in a support layer (2) is a position such that the front face of the first component is not covered and lies parallel to a first face of the support layer. An intermediate layer (8) is formed on the front face of the first component and on the first face of the support layer. An electrical connection network (9) within the intermediate layer selectively connects to the electrical connection pads of the first component. The device further includes at least one second component (11) (for example, a second integrate circuit, having one face placed above the intermediate layer and provided with electrical connection pads selectively connected to the electrical connection network.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: July 9, 2013
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics S.r.l.
    Inventors: Romain Coffy, Remi Brechignac, Carlo Cognetti de Martiis
  • Publication number: 20130012276
    Abstract: An electronic package includes a substrate wafer having front and rear faces. An emitting integrated circuit chip is mounted to the front face of the substrate wafer and includes a light radiation optical emitter. A receiving integrated circuit chip is also mounted to the front face of the substrate wafer and includes at least one light radiation optical sensor. A transparent encapsulant extends above the optical sensor and the optical emitter. An opaque encapsulant encapsulates the transparent encapsulant. The opaque encapsulant has a front window situated above the optical emitter and which is offset laterally relative to the optical sensor. The transparent encapsulant accordingly has an uncovered front face situated above the optical emitter and offset laterally relative to the optical sensor. The opaque encapsulant may include an additional front window. The receiving integrated circuit chip further includes a second optical sensor situated opposite the additional front window.
    Type: Application
    Filed: July 3, 2012
    Publication date: January 10, 2013
    Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Romain Coffy, Remi Brechignac
  • Publication number: 20110248397
    Abstract: A semiconductor device includes at least one first component (5) (for example, a first integrated circuit), having a front face provided with electrical connection pads. The first component is embedded in a support layer (2) is a position such that the front face of the first component is not covered and lies parallel to a first face of the support layer. An intermediate layer (8) is formed on the front face of the first component and on the first face of the support layer. An electrical connection network (9) within the intermediate layer selectively connects to the electrical connection pads of the first component. The device further includes at least one second component (11) (for example, a second integrate circuit, having one face placed above the intermediate layer and provided with electrical connection pads selectively connected to the electrical connection network.
    Type: Application
    Filed: November 10, 2009
    Publication date: October 13, 2011
    Applicants: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (GRENOBLE) SAS
    Inventors: Romain Coffy, Remi Brechignac, Carlo Cognetti De Martiis
  • Patent number: 7327005
    Abstract: An optical semiconductor module including an optical semiconductor component that has a front face including an optical sensor. Encapsulation, defining a cavity in which the optical component is disposed, includes external electrical connections for the optical semiconductor component, and includes a window allowing light to pass through it toward the optical sensor. An optical lens (17) is disposed in the cavity (6) between the optical sensor (10) and the window (5). A support structure (18) supports the optical lens. This optical semiconductor module may also include a shield (24).
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: February 5, 2008
    Assignee: STMicroelectronics SA
    Inventors: Remi Brechignac, Juan Exposito