Abstract: A charge pump controller (20) comprises a configurable pump capacitor (15, 16). A charge pump controller (20) controls the charge supplied to a load (12) to be less than the charge stored on the pump capacitor (15, 16).

Abstract: A charge pump controller (20) comprises a configurable pump capacitor (15, 16). A charge pump controller (20) controls the charge supplied to a load (12) to be less than the charge stored on the pump capacitor (15, 16).

Abstract: In one embodiment, a switch capacitor controller (20) is configured to use a drive signal (45) to drive the switched capacitor (26) with a signal having a time dependent transition time.

Abstract: In one embodiment a switched capacitor dc-dc converter uses the load current to assist in determining a supply configuration to use to form the output voltage.

Abstract: In one embodiment a switched capacitor dc-dc converter uses the load current to assist in determining a supply configuration to use to form the output voltage.

Abstract: In one embodiment, a switch capacitor controller (20) is configured to use a drive signal (45) to drive the switched capacitor (26) with a signal having a time dependent transition time.

Abstract: A circuit for reducing leakage current through one or more output transistors (312) includes a capacitor circuit (302) and additional circuitry. The capacitor circuit (302) stores and discharges a charge, thus providing a current having a limited duration, which is related to a discharge time of the capacitor circuit. In one embodiment, the additional circuitry includes a current source circuit (304), an amplifier circuit (307), and one or more transistors (308, 310). The current source circuit is temporarily activated by the current from the capacitor circuit, and provides a second current to the amplifier circuit. The amplifier circuit amplifies the second current, and the amplifier current is used to activate the transistors (308, 310). When activated, the transistors draw current from the control terminals (e.g., the bases) of the output transistors (312) after the output transistors have been switched off, thus reducing leakage currents through the output transistors.

Abstract: A circuit for reducing leakage current through one or more output transistors (312) includes a capacitor circuit (302) and additional circuitry. The capacitor circuit (302) stores and discharges a charge, thus providing a current having a limited duration, which is related to a discharge time of the capacitor circuit. In one embodiment, the additional circuitry includes a current source circuit (304), an amplifier circuit (307), and one or more transistors (308, 310). The current source circuit is temporarily activated by the current from the capacitor circuit, and provides a second current to the amplifier circuit. The amplifier circuit amplifies the second current, and the amplifier current is used to activate the transistors (308, 310). When activated, the transistors draw current from the control terminals (e.g., the bases) of the output transistors (312) after the output transistors have been switched off, thus reducing leakage currents through the output transistors.

Abstract: A high/low and low/high analogue level converter circuit for integrated circuits in which a high/low converter circuit comprises, supplied at a first voltage value, a converter module which receives a logic input signal of analogue level adapted to this first voltage value and delivers a logic signal inverted and replicated with analogue level adapted to this first voltage value, and, supplied at a second voltage value, a differential converter module which from inverted and replicated logic signals delivers a converted logic input signal with analogue level adapted to second voltage value.

Abstract: A symmetric adapter unit for switching a logic signal implemented in CMOS technology that includes a control module for transmission and non-transmission of the logic signal, receiving this logic signal and a control logic signal to deliver a first and a second asymmetric switching control signal. A bistable type switching module receives the first and the second switching control signal and delivers a logic signal adapted in phase with the logic signal or a substantially constant signal to the output terminal, constituting a high impedance output.

Abstract: A device that generates a DC reference voltage approximately equal to half a DC supply voltage. It includes an input stage forming a first potentiometric divider comprising two branches having an asymmetric behavior in response to variations in the room and/or operating temperature, and supplying a first DC voltage (NBGP), an intermediate stage forming a resistive and capacitive filter, which eliminates the dynamic component of the first DC voltage (NGBP) and supplies a second DC voltage (NARF), and an output stage forming a second potentiometric divider comprising two branches also having an asymmetric behavior of which the voltage variations are smaller than those of the first divider comprising in addition a logic inverter function, and supplying a third DC voltage (NREF), the variations of which are the inverse of those in the second DC voltage (NARF), the variations in the latter being thus compensated.

Abstract: A device for interfacing from the LLL level to the TTL and CMOS level that comprises, in cascade, a first and a second amplifier-inverter and a shaping circuit delivering an inverted logic signal at the TTL level. A power inverter-amplifier circuit receives the inverted logic signal at the TTL level and delivers an amplified logic signal at the TTL level.

Abstract: An ECL level/CMOS level logic signal interfacing device includes, connected in cascade, a circuit for generating an in-phase relationship with an ECL level input signal, a threshold inverter circuit receiving the in-phase signal at an inverter input and delivering an inverted in-phase signal, a shaping inverter circuit receiving the inverted in-phase signal and outputting a calibrated in-phase signal, and an output amplifier circuit receiving the calibrated in-phase signal and outputting an output signal to the CMOS level in phase relationship with the ECL level input signal. The circuits are supplied with a CMOS level supply voltage relative to a reference voltage.

Abstract: This analog-digital conversion device comprises switching means (CS) having two close and centered triggering thresholds; a NOR logic gate (PL) which, when the conversion device is not being used, receives a standby command signal and delivers a zero digital output signal (NOUT) imposed on the input (NIN) of the switching means (CS); preamplification means (PS); and amplification means (AS) receiving a standby command signal and delivering either the digital output signal (NOUT), in the absence of a standby command, or a zero-value signal in the event of a standby command.

Abstract: A three-state output interfacing device for a CMOS memory that comprises a stage for selective control of the device, receiving an input signal (I) at the bit frequency and a control signal (e) and making it possible to deliver, on two ports (A) and (B), either complemented signals (I), or distinct logic levels for driving the device into the high-impedance state, a first inverter stage delivering first inverted logic signals, from the ports (A) and (B), on two ports (C) and (D), a second inverter stage delivering second inverted signals from the ports (C) and (D), a stage for reducing the analog difference between the second inverted signals and for switching the output interfacing device into high-impedance state at ports (E) and (F), and an output stage receiving the signals from the ports (E) and (F) after reduction of analog difference and making it possible to fix and balance the current for charging and discharging the output capacitance of the output interfacing device and its high-impedance switching