Patents by Inventor Remi Marius TEYSSIER
Remi Marius TEYSSIER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11537522Abstract: An apparatus is provided for determining, for use in a tag-guarded memory, a selected tag value from a plurality of tag values. The apparatus comprises ordered list generation circuitry to receive an excluded tag vector comprising a plurality of fields, where each field is associated with a tag value and identifies whether the associated tag value is excluded from use. The ordered list generation circuitry is arranged to generate, from the excluded tag vector, an ordered list of non-excluded tag values. The apparatus further comprises count determination circuitry to determine, using the excluded tag vector and an identified start tag value, a count value indicative of a number of non-excluded tag values occurring in a region of the excluded tag vector bounded by an initial field and a field corresponding to the start tag value.Type: GrantFiled: July 25, 2019Date of Patent: December 27, 2022Assignee: Arm LimitedInventors: Xiaoyang Shen, Yohann Fred Arifidy Rabefarihy, Cédric Denis Robert Airaud, Rémi Marius Teyssier
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Patent number: 11157277Abstract: Data processing apparatus comprises a processing element configured to access an architectural register representing a given system register; mapping circuitry to map the architectural register representing the given system register to a physical register selected from a set of physical registers; a register bank having a set of two or more respective banked versions of the given system register, in which a respective one of the banked versions of the system register is associated with each of a plurality of current operating states of the processing element; in which, when the processing element changes operating state from a first operating state associated with a first one of the banked versions of the system register to a second operating state associated with a second, different, one of the banked versions of the system register, the processing element is configured to store the current contents of the architectural register representing the given system register to the first one of the banked versions oType: GrantFiled: September 5, 2019Date of Patent: October 26, 2021Assignee: Arm LimitedInventors: Cedric Denis Robert Airaud, Albin Pierrick Tonnerre, Luca Nassi, Remi Marius Teyssier
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Patent number: 11132202Abstract: An apparatus comprises execution circuitry to perform operations on source data values and to generate result data values; issue circuitry comprising one or more issue queues identifying pending operations awaiting performance by the execution circuitry, and selection circuitry to select pending operations to issue to the execution circuitry; data value cache storage comprising first and second cache regions; and cache control circuitry to control the storing to the first cache region of result data values generated by the execution circuitry and the eviction of stored result data values from the first cache region in response to newly generated result data values being stored in the first cache region; the cache control circuitry being configured to store to the second cache region result data values required as source data values for one or more oldest pending operations identified by the one or more issue queues and to inhibit eviction of a given result data value stored in the second cache region until inType: GrantFiled: September 24, 2019Date of Patent: September 28, 2021Assignee: Arm LimitedInventors: Luca Nassi, Rémi Marius Teyssier, Cédric Denis Robert Airaud, Albin Pierrick Tonnerre, Francois Donati, Christophe Carbonne, Damian Maiorano
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Patent number: 10977044Abstract: An apparatus comprising processing circuitry is provided, the processing circuitry comprising execution circuitry, commit circuitry, issue circuitry comprising an issue queue and selection circuitry, and a branch predictor. The processing circuitry is configured to identify a speculation barrier instruction in the commit queue. While an entry in the commit queue identifies a speculation barrier instruction, when a branch instruction that follows the speculation barrier instruction in the program order is selected for issue, the processing circuitry performs a first execution of the instruction, inhibiting updating of branch prediction data items associated with the branch instruction and inhibiting the selection circuitry from invalidating the associated issue queue entry.Type: GrantFiled: September 5, 2019Date of Patent: April 13, 2021Assignee: Arm LimitedInventors: Remi Marius Teyssier, Luca Nassi, Albin Pierrick Tonnerre, François Donati
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Patent number: 10915327Abstract: Aspects of the present disclosure relate to an apparatus comprising a plurality of clusters, each cluster having a plurality of execution units to execute instructions. The apparatus comprises dispatch circuitry to determine, for each instruction to be executed, a chosen cluster from amongst the plurality of clusters to which to dispatch that instruction for execution. This determination is performed by selecting between a default dispatch policy wherein said chosen cluster is a cluster to which an earlier instruction to generate at least one source operand of said instruction was dispatched for execution, and an alternative dispatch policy for selecting said chosen cluster. Said selecting is based on a selection parameter. The dispatch circuitry is further configured to dispatch said instruction to the chosen cluster for execution.Type: GrantFiled: December 14, 2018Date of Patent: February 9, 2021Assignee: Arm LimitedInventors: Luca Nassi, Remi Marius Teyssier, François Donati, Damian Maiorano
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Publication number: 20210026772Abstract: An apparatus is provided for determining, for use in a tag-guarded memory, a selected tag value from a plurality of tag values. The apparatus comprises ordered list generation circuitry to receive an excluded tag vector comprising a plurality of fields, where each field is associated with a tag value and identifies whether the associated tag value is excluded from use. The ordered list generation circuitry is arranged to generate, from the excluded tag vector, an ordered list of non-excluded tag values. The apparatus further comprises count determination circuitry to determine, using the excluded tag vector and an identified start tag value, a count value indicative of a number of non-excluded tag values occurring in a region of the excluded tag vector bounded by an initial field and a field corresponding to the start tag value.Type: ApplicationFiled: July 25, 2019Publication date: January 28, 2021Inventors: Xiaoyang SHEN, Yohann Fred Arifidy RABEFARIHY, Cédric Denis Robert AIRAUD, Rémi Marius TEYSSIER
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Publication number: 20200192674Abstract: Aspects of the present disclosure relate to an apparatus comprising a plurality of clusters, each cluster having a plurality of execution units to execute instructions. The apparatus comprises dispatch circuitry to determine, for each instruction to be executed, a chosen cluster from amongst the plurality of clusters to which to dispatch that instruction for execution. This determination is performed by selecting between a default dispatch policy wherein said chosen cluster is a cluster to which an earlier instruction to generate at least one source operand of said instruction was dispatched for execution, and an alternative dispatch policy for selecting said chosen cluster. Said selecting is based on a selection parameter. The dispatch circuitry is further configured to dispatch said instruction to the chosen cluster for execution.Type: ApplicationFiled: December 14, 2018Publication date: June 18, 2020Inventors: Luca NASSI, Remi Marius TEYSSIER, François DONATI, Damian MAIORANO
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Patent number: 10635445Abstract: An apparatus and method of operating an apparatus are disclosed. The apparatus has a program counter permitted range storage element defining a permitted range of program counter values for the sequence of instructions it executes. Branch prediction circuitry predicts target instruction addresses for branch instructions. In response to a program counter modifying event, a program counter speculative range storage element is updated corresponding to each speculatively executed instruction after a branch instruction. Program counter permitted range verification circuitry is responsive to resolution of a modification of the program counter permitted range indication resulting from the program counter modifying event to determine whether the speculatively executed program counter range satisfies the permitted range of program counter values. A branch mis-prediction mechanism may support the response of the apparatus if the permitted range of program counter values is violated.Type: GrantFiled: May 29, 2018Date of Patent: April 28, 2020Assignee: Arm LimitedInventors: Rémi Marius Teyssier, Albin Pierrick Tonnerre, Cédric Denis Robert Airaud, Luca Nassi, Guillaume Bolbenes, Francois Donati, Lee Evan Eisen, Pasquale Ranone
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Publication number: 20200117463Abstract: An apparatus comprises execution circuitry to perform operations on source data values and to generate result data values; issue circuitry comprising one or more issue queues identifying pending operations awaiting performance by the execution circuitry, and selection circuitry to select pending operations to issue to the execution circuitry; data value cache storage comprising first and second cache regions; and cache control circuitry to control the storing to the first cache region of result data values generated by the execution circuitry and the eviction of stored result data values from the first cache region in response to newly generated result data values being stored in the first cache region; the cache control circuitry being configured to store to the second cache region result data values required as source data values for one or more oldest pending operations identified by the one or more issue queues and to inhibit eviction of a given result data value stored in the second cache region until inType: ApplicationFiled: September 24, 2019Publication date: April 16, 2020Inventors: Luca NASSI, Rémi Marius TEYSSIER, Cédric Denis Robert AIRAUD, Albin Pierrick TONNERRE, Francois DONATI, Christophe CARBONNE, Damian MAIORANO
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Publication number: 20200117464Abstract: An apparatus comprising processing circuitry is provided, the processing circuitry comprising execution circuitry, commit circuitry, issue circuitry comprising an issue queue and selection circuitry, and a branch predictor. The processing circuitry is configured to identify a speculation barrier instruction in the commit queue. While an entry in the commit queue identifies a speculation barrier instruction, when a branch instruction that follows the speculation barrier instruction in the program order is selected for issue, the processing circuitry performs a first execution of the instruction, inhibiting updating of branch prediction data items associated with the branch instruction and inhibiting the selection circuitry from invalidating the associated issue queue entry.Type: ApplicationFiled: September 5, 2019Publication date: April 16, 2020Inventors: Remi Marius TEYSSIER, Luca NASSI, Albin Pierrick TONNERRE, François DONATI
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Publication number: 20200110613Abstract: Data processing apparatus comprises a processing element configured to access an architectural register representing a given system register; mapping circuitry to map the architectural register representing the given system register to a physical register selected from a set of physical registers; a register bank having a set of two or more respective banked versions of the given system register, in which a respective one of the banked versions of the system register is associated with each of a plurality of current operating states of the processing element; in which, when the processing element changes operating state from a first operating state associated with a first one of the banked versions of the system register to a second operating state associated with a second, different, one of the banked versions of the system register, the processing element is configured to store the current contents of the architectural register representing the given system register to the first one of the banked versions oType: ApplicationFiled: September 5, 2019Publication date: April 9, 2020Inventors: Cedric Denis Robert AIRAUD, Albin Pierrick TONNERRE, Luca NASSI, Remi Marius TEYSSIER
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Patent number: 10558462Abstract: An apparatus and method are provided for storing source operands for operations. The apparatus comprises execution circuitry for performing operations on data values, and a register file comprising a plurality of registers to store the data values operated on by the execution circuitry. Issue circuitry is also provided that has a pending operations storage identifying pending operations awaiting performance by the execution circuitry and selection circuitry to select pending operations from the pending operation storage to issue to the execution circuitry. The pending operations storage comprises an entry for each pending operation, each entry storing attribute information identifying the operation to be performed, where that attribute information includes a source identifier field for each source operand of the pending operation.Type: GrantFiled: May 23, 2018Date of Patent: February 11, 2020Assignee: Arm LimitedInventors: Luca Nassi, Cédric Denis Robert Airaud, Rémi Marius Teyssier, Albin Pierrick Tonnerre
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Publication number: 20190370001Abstract: An apparatus and method of operating an apparatus are disclosed. The apparatus has a program counter permitted range storage element defining a permitted range of program counter values for the sequence of instructions it executes. Branch prediction circuitry predicts target instruction addresses for branch instructions. In response to a program counter modifying event, a program counter speculative range storage element is updated corresponding to each speculatively executed instruction after a branch instruction. Program counter permitted range verification circuitry is responsive to resolution of a modification of the program counter permitted range indication resulting from the program counter modifying event to determine whether the speculatively executed program counter range satisfies the permitted range of program counter values. A branch mis-prediction mechanism may support the response of the apparatus if the permitted range of program counter values is violated.Type: ApplicationFiled: May 29, 2018Publication date: December 5, 2019Inventors: Rémi Marius TEYSSIER, Albin Pierrick TONNERRE, Cédric Denis Robert AIRAUD, Luca NASSI, Guillaume BOLBENES, Francois DONATI, Lee Evan EISEN, Pasquale RANONE
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Publication number: 20190361705Abstract: An apparatus and method are provided for storing source operands for operations. The apparatus comprises execution circuitry for performing operations on data values, and a register file comprising a plurality of registers to store the data values operated on by the execution circuitry. Issue circuitry is also provided that has a pending operations storage identifying pending operations awaiting performance by the execution circuitry and selection circuitry to select pending operations from the pending operation storage to issue to the execution circuitry. The pending operations storage comprises an entry for each pending operation, each entry storing attribute information identifying the operation to be performed, where that attribute information includes a source identifier field for each source operand of the pending operation.Type: ApplicationFiled: May 23, 2018Publication date: November 28, 2019Inventors: Luca NASSI, Cédric Denis Robert AIRAUD, Rémi Marius TEYSSIER, Albin Pierrick TONNERRE