Abstract: Coupling device for the connection of a Data Circuit Terminating Equipment DCE to a given Public Switched Telephone Network PSTN and to a local telephone set. The coupler includes means for providing said local telephone set with DC current whereby the microphone and the headphone of the telephone can be used respectively for transmitting and receiving vocal messages from the a DTE which is connected to said DCE. The invention also provides a DCE for the connection of a DTE to a a PSTN and to a local telephone set including a coupler circuit having the electronic components matching the electric requirements of a given PSTN. The coupler further includes means for providing the telephone set with DC current whereby vocal messages can be transmitted and received from the DTE to the telephone set.

Abstract: The programmable logic controller uses a set of instructions which comprises only three instructions: a Read instruction and a Write instruction which includes an operation code, a condition bit, and an address, and a Jump instruction which includes an operation code and an address. When a Read instruction is read from control memory (10), a condition latch (35) is set to 1 or 0 depending on whether the level of the addressed input corresponds or not to the level of the condition bit. For a Write operation, the state of latch (35) or its inverse is provided at the addressed output in accordance with the value of the condition bit. A Jump instruction is executed only if the condition latch (35) is set to 1. A random access memory (50) may be utilized to function as one of the input multiplexers (RI0 to RI2) and one of the output demultiplexers (RO0 to RO2), which allows the controller to store events and to use said events later on.

Abstract: A pulse generating device for speeding-up the rate of a pulse train from N to N+n wherein each of the pulses in the N+n pulse train is synchronized with the immediately preceding pulse in the original N pulse train. A count-up counter is reset upon each original pulse and counts up from zero, at frequency F/N+n, up to the following original pulse. A count-down counter is loaded with the contents of the count-up counter when the following original pulse occurs or when the output pulses occur with the exception of the last pulse in the interval when the time interval between said original pulses includes several generated output pulses, and is decremented at frequency F/M up to zero. A variable presettable counter provides the count-down counter with frequency F/M when each original pulse appears or when the output pulses appear with the exception of the last pulse in the interval when the time interval between the original pulses includes several output pulses.

Abstract: The structure described is a switching-processing node for high speed data transmission systems. Information is transmitted in time slot channels, one of which is control information. Data to be passed through a node is stripped of control characters, passed to a transmitting unit and there re-encoded with such additional data bits as needed. Data for the node is switched from an input decoder to a processor input and data for transmission is switched to a transmission unit for encoding.A switching information control frame can be passed over the system to set the switching circuits at a node to operate at the appropriate time slots of the data frames.