Patents by Inventor Ren-Chyi You

Ren-Chyi You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11507067
    Abstract: A method is disclosed that includes the operations below: determining, by a processing unit, that arrival times of a lot arrived at N process stages are less than processing times of the lot predetermined to be processed at the N process stages, N being a positive integer; comparing, by the processing unit, idle times of multiple tools in the N process stages; and processing the lot with a first tool of the tools at each one of the N process stages, wherein the first tool of the tools has a shortest idle time.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ren-Chyi You, An-Wei Peng, Chang-Zong Liu, Yuang-Tsung Chen
  • Publication number: 20210089012
    Abstract: A system includes a dispatching system and at least one processor. The dispatching system is configured to provide dispatching preferences indicating that tools feedback preferences thereof for at least one lot. The processor is coupled to the dispatching system and at least one memory. Computer program code encoded in the memory is executed by the processor to cause the system to process the lot using at least one of the tools with utilization of a tool-lot relationship that is generated based on the dispatching preferences. A non-transitory computer readable medium and a method are also disclosed herein.
    Type: Application
    Filed: December 6, 2020
    Publication date: March 25, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ren-Chyi YOU, An-Wei PENG, Chang-Zong LIU, Jun-Sheng YEH
  • Patent number: 10860008
    Abstract: A method is disclosed and includes generating a tool-lot relationship based on at least one process constraint and a dispatching rule which includes dispatching preferences for operating at least one lot; assigning the at least one lot to at least one tool by using the tool-lot relationship; and the at least one tool, assigned using the tool-lot relationship, processing the at least one lot by utilization of the tool-lot relationship to manufacture semiconductor devices on at least one wafer in the at least one lot.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ren-Chyi You, An-Wei Peng, Chang-Zong Liu, Jun-Sheng Yeh
  • Publication number: 20200333771
    Abstract: A method is disclosed that includes the operations below: determining, by a processing unit, that arrival times of a lot arrived at N process stages are less than processing times of the lot predetermined to be processed at the N process stages, N being a positive integer; comparing, by the processing unit, idle times of multiple tools in the N process stages; and processing the lot with a first tool of the tools at each one of the N process stages, wherein the first tool of the tools has a shortest idle time.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ren-Chyi YOU, An-Wei PENG, Chang-Zong LIU, Yuang-Tsung CHEN
  • Patent number: 10719067
    Abstract: A method is disclosed that includes the operations below: comparing an arrival time of a lot arrived at a process stage of N process stages with a processing time, determining whether one of tools at the process stage has a remain operation time which is equal to, or less than and closest to the arrival time, when a first tool of the tools has a first remain operation time which is equal to, or less than and closest to the arrival time, processing the lot with the first tool of the tools in the process stage after dispatching the lot to the processing stage, and generating at least one semiconductor device from the lot based on the comparing, determining and processing.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ren-Chyi You, An-Wei Peng, Chang-Zong Liu, Yuang-Tsung Chen
  • Publication number: 20190250594
    Abstract: A method is disclosed that includes the operations below: comparing an arrival time of a lot arrived at a process stage of N process stages with a processing time, determining whether one of tools at the process stage has a remain operation time which is equal to, or less than and closest to the arrival time, when a first tool of the tools has a first remain operation time which is equal to, or less than and closest to the arrival time, processing the lot with the first tool of the tools in the process stage after dispatching the lot to the processing stage, and generating at least one semiconductor device from the lot based on the comparing, determining and processing.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ren-Chyi YOU, An-Wei PENG, Chang-Zong LIU, Yuang-Tsung CHEN
  • Publication number: 20190137981
    Abstract: A method is disclosed and includes generating a tool-lot relationship based on at least one process constraint and a dispatching rule which includes dispatching preferences for operating at least one lot; assigning the at least one lot to at least one tool by using the tool-lot relationship; and the at least one tool, assigned using the tool-lot relationship, processing the at least one lot by utilization of the tool-lot relationship to manufacture semiconductor devices on at least one wafer in the at least one lot.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ren-Chyi YOU, An-Wei PENG, Chang-Zong LIU, Jun-Sheng YEH
  • Patent number: 10268186
    Abstract: A method is disclosed that includes the operations below. A lot is dispatched for N process stages of process stages, according to arrival durations of the lot arrived at the N process stages and process durations of the lot predetermined to be processed at the N process stages, in which N is a positive integer. A first tool of tools at each one of the N process stages are assigned for the lot, in which the lot is configured to be dispatched to the first tool at a first process stage of the N process stages according to a first arrival duration of the arrival durations of the lot arrived at the first process stage and remain operation durations of the tools at the first process stage.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ren-Chyi You, An-Wei Peng, Chang-Zong Liu, Yuang-Tsung Chen
  • Patent number: 10162340
    Abstract: A method is disclosed and includes determining whether there is any WIP information with one or more process constraints in a process constraint database that is coupled with a manufacturing execution system; determining whether there is a dispatching rule in the dispatching rule database that is coupled with a dispatching system; generating a tool-lot relationship based on at least one of the process constraints and the dispatching rule; utilizing the tool-lot relationship to assign one or more lots to one or more tools respectively.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ren-Chyi You, An-Wei Peng, Chang-Zong Liu, Jun-Sheng Yeh
  • Publication number: 20170090465
    Abstract: A method is disclosed and includes determining whether there is any WIP information with one or more process constraints in a process constraint database that is coupled with a manufacturing execution system; determining whether there is a dispatching rule in the dispatching rule database that is coupled with a dispatching system; generating a tool-lot relationship based on at least one of the process constraints and the dispatching rule; utilizing the tool-lot relationship to assign one or more lots to one or more tools respectively.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: Ren-Chyi YOU, An-Wei PENG, Chang-Zong LIU, Jun-Sheng YEH
  • Publication number: 20160091891
    Abstract: A method is disclosed that includes the operations below. A lot is dispatched for N process stages of process stages, according to arrival durations of the lot arrived at the N process stages and process durations of the lot predetermined to be processed at the N process stages, in which N is a positive integer. A first tool of tools at each one of the N process stages are assigned for the lot, in which the lot is configured to be dispatched to the first tool at a first process stage of the N process stages according to a first arrival duration of the arrival durations of the lot arrived at the first process stage and remain operation durations of the tools at the first process stage.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 31, 2016
    Inventors: Ren-Chyi YOU, An-Wei PENG, Chang-Zong LIU, Yuang-Tsung CHEN
  • Patent number: 7925380
    Abstract: System and method for implementing integrated transportation control in a wafer fabrication facility are described. One embodiment is a factory automation system for a wafer fabrication facility (“fab”) comprising a plurality of bays, wherein each of the bays comprise a plurality of equipment interconnected by an intrabay overhead transport (“OHT”) system, and first and second interbay OHT systems each for interconnecting the intrabay OHT systems. The factory automation system comprises a manufacturing execution system (“MES”) for providing lot information regarding wafers being processed in the fab, a material control system (“MCS”) for providing traffic information regarding transportation of wafers in the fab, and an integrated transportation control (“ITC”) system for using the lot information from the MES and the traffic information from the MCS for selecting a destination and a route to the selected destination for a wafer carrier containing wafers in response to a transfer request.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: April 12, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yuan Yu, Ren-Chyi You, Ming Wang
  • Publication number: 20080021593
    Abstract: System and method for implementing integrated transportation control in a wafer fabrication facility are described. One embodiment is a factory automation system for a wafer fabrication facility (“fab”) comprising a plurality of bays, wherein each of the bays comprise a plurality of equipment interconnected by an intrabay overhead transport (“OHT”) system, and first and second interbay OHT systems each for interconnecting the intrabay OHT systems. The factory automation system comprises a manufacturing execution system (“MES”) for providing lot information regarding wafers being processed in the fab, a material control system (“MCS”) for providing traffic information regarding transportation of wafers in the fab, and an integrated transportation control (“ITC”) system for using the lot information from the MES and the traffic information from the MCS for selecting a destination and a route to the selected destination for a wafer carrier containing wafers in response to a transfer request.
    Type: Application
    Filed: July 19, 2006
    Publication date: January 24, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yuan YU, Ren-Chyi YOU, Ming WANG
  • Patent number: 6647307
    Abstract: An algorithm can be performed to control the dispatch of products in a fabrication or manufacturing facility. The queue time constraint tolerances and tool throughput are initialized for each product. Next the multiple processing demand time can be calculated for each product. The aggregating queue time constraint can then be calculated for each product. If the multiple processing demand time is less than the aggregating queue time constraint for each queue time limit tool, then any lot can be selected to be processed. Otherwise, the product at the given tool should be further processed.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: November 11, 2003
    Assignee: Taiwan Semiconductor Mfg. Co. Ltd.
    Inventors: Liang-Kai Huang, Span Lu, Ren-Chyi You, Kuang-Huan Hsu