Patents by Inventor Ren-Hong Luo

Ren-Hong Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031936
    Abstract: A hybrid transmitter includes a current-mode driver, a voltage-mode driver and an auxiliary driver. The current-mode driver is configured to perform a current transmission. The voltage-mode driver is configured to perform a voltage transmission. The auxiliary driver, coupled to the current-mode driver and the voltage-mode driver, is configured to cooperate with the current-mode driver to enhance a driving capability of the current transmission and cooperate with the voltage-mode driver to enhance a driving capability of the voltage transmission.
    Type: Grant
    Filed: April 19, 2020
    Date of Patent: June 8, 2021
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Ren-Hong Luo, Kun-Jui Shen, Ying-Cheng Lin
  • Patent number: 10614766
    Abstract: A voltage regulator and method applied thereto are provided. The voltage regulator generates a regulated voltage in response to a reference voltage and a control code. The voltage regulator includes a voltage divider circuit, an amplifier circuit, and a power MOS array. The voltage divider circuit is configured to divide the regulated voltage to generate a feedback voltage. The amplifier circuit is configured to amplify a voltage difference between the reference voltage and the feedback voltage to generate a bias voltage. The power MOS array includes multiple transistors. Each transistor has a first terminal coupled to a power rail, a second terminal coupled to the regulated voltage, and a control terminal selectively coupled to either the power rail or the bias voltage in response to the control code.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: April 7, 2020
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Ren-Hong Luo, Shih-Chun Lin, Yung-Cheng Lin, Mu-Jung Chen
  • Publication number: 20170337886
    Abstract: A voltage regulator and method applied thereto are provided. The voltage regulator generates a regulated voltage in response to a reference voltage and a control code. The voltage regulator includes a voltage divider circuit, an amplifier circuit, and a power MOS array. The voltage divider circuit is configured to divide the regulated voltage to generate a feedback voltage. The amplifier circuit is configured to amplify a voltage difference between the reference voltage and the feedback voltage to generate a bias voltage. The power MOS array includes multiple transistors. Each transistor has a first terminal coupled to a power rail, a second terminal coupled to the regulated voltage, and a control terminal selectively coupled to either the power rail or the bias voltage in response to the control code.
    Type: Application
    Filed: May 19, 2016
    Publication date: November 23, 2017
    Applicant: NOVATEK MICROELECTRONICS CORP.
    Inventors: Ren-Hong LUO, Shih-Chun LIN, Yung-Cheng LIN, Mu-Jung CHEN
  • Patent number: 9800265
    Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: October 24, 2017
    Assignee: Novatek Microelectronics Corp.
    Inventors: Shih-Chun Lin, Ren-Hong Luo, Mu-Jung Chen, Yung-Cheng Lin
  • Publication number: 20170279461
    Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.
    Type: Application
    Filed: January 18, 2017
    Publication date: September 28, 2017
    Applicant: Novatek Microelectronics Corp.
    Inventors: Shih-Chun Lin, Ren-Hong Luo, Mu-Jung Chen, Yung-Cheng Lin
  • Patent number: 9515699
    Abstract: A dual mode serial transmission apparatus and method for switching a mode thereof are provided. The dual mode serial transmission apparatus includes a first and second current sources, a first and second inverting circuits, a differential pair and a resistor string. The first inverting circuit receives a mode selecting signal or a first data transmission signal, the second inverting circuit receives the mode selecting signal or a second data transmission signal. First and second load terminals of the differential pair are respectively coupled to the first and second inverting circuits. A common terminal of the differential pair is coupled to the second current source. First and second differential input terminals receive the mode selecting signal or respectively receive the first and second data transmission signals. The resistor string is coupled in series between output terminals of the first and second inverting circuits.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: December 6, 2016
    Assignee: Novatek Microelectronics Corp.
    Inventors: Ren-Hong Luo, Yan-Ting Wang, Hsiang-Chi Li, Mu-Jung Chen
  • Publication number: 20160226557
    Abstract: A dual mode serial transmission apparatus and method for switching a mode thereof are provided. The dual mode serial transmission apparatus includes a first and second current sources, a first and second inverting circuits, a differential pair and a resistor string. The first inverting circuit receives a mode selecting signal or a first data transmission signal, the second inverting circuit receives the mode selecting signal or a second data transmission signal. First and second load terminals of the differential pair are respectively coupled to the first and second inverting circuits. A common terminal of the differential pair is coupled to the second current source. First and second differential input terminals receive the mode selecting signal or respectively receive the first and second data transmission signals. The resistor string is coupled in series between output terminals of the first and second inverting circuits.
    Type: Application
    Filed: May 27, 2015
    Publication date: August 4, 2016
    Inventors: Ren-Hong Luo, Yan-Ting Wang, Hsiang-Chi Li, Mu-Jung Chen
  • Publication number: 20120280696
    Abstract: A chip test system including a chip under test, a test chip, and a test equipment is provided. The chip under test receives a test input data and provides a test output data according to the test input data. The test chip performs at least one of a skew test, a jitter test, and a setup/hold time test on the chip under test by using the test input data and determines whether a test result falls within a predetennined range. The test equipment provides the test input data and inputs the test input data into the chip under test through the test chip.
    Type: Application
    Filed: July 6, 2011
    Publication date: November 8, 2012
    Applicant: NOVATEK MICROELECTRONICS CORP.
    Inventor: Ren-Hong Luo
  • Patent number: 7564281
    Abstract: A wide-locking range phase locked loop circuit includes a decision unit and a closed loop connection comprising a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a multi-modulus divider. The decision unit receives a phase difference signal outputted from phase frequency detector and the control voltage outputted from the loop filter and determines to select a specific divisor form the plurality of divisors provided by the multi-modulus divider if the phase difference signal indicates an unlocked state and the control voltage is not within a standard voltage operation range.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: July 21, 2009
    Assignee: Faraday Technology Corporation
    Inventors: Ren-Hong Luo, Cheng-Ta Wei
  • Publication number: 20090037695
    Abstract: A data fetch circuit and a method thereof are provided. A multi-phase clock signal is generated according to an input clock, and an input data is over-sampled according to the multi-phase clock signal in order to detect transition points of the input data. One of reference phases of the multi-phase clock signal is selected according to the detected transition point for fetching the input data and obtaining enough setup/hold time margin. Accordingly, appropriate data fetch points is found without complicated negative feed-back mechanism. Besides, a periodical monitoring mechanism may be further adopted for improving the accuracy of data fetch.
    Type: Application
    Filed: August 3, 2007
    Publication date: February 5, 2009
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventor: Ren-Hong Luo
  • Publication number: 20080174349
    Abstract: A wide-locking range phase locked loop circuit includes a decision unit and a closed loop connection comprising a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a multi-modulus divider. The decision unit receives a phase difference signal outputted from phase frequency detector and the control voltage outputted from the loop filter and determines to select a specific divisor form the plurality of divisors provided by the multi-modulus divider if the phase difference signal indicates an unlocked state and the control voltage is not within a standard voltage operation range.
    Type: Application
    Filed: January 18, 2008
    Publication date: July 24, 2008
    Applicant: FARADAY TECHNOLOGY CORPORATION
    Inventors: Ren-Hong Luo, Cheng-Ta Wei