Patents by Inventor Ren-Hua GUO
Ren-Hua GUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11930628Abstract: A device includes a substrate, a pull-down transistor over the substrate, a pass-gate transistor over the substrate, and a pull-up transistor over the substrate. The pull-up transistor includes a first gate structure and first source/drain epitaxy structures on opposite sides of the first gate structure, in which each of the first source/drain epitaxy structures comprises a first epitaxy layer and a second epitaxy layer over the first epitaxy layer, wherein a germanium concentration of the first epitaxy layer is higher than a germanium concentration of the second epitaxy layer.Type: GrantFiled: April 3, 2023Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-I Shih, Ren-Hua Guo
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Publication number: 20230247818Abstract: A device includes a substrate, a pull-down transistor over the substrate, a pass-gate transistor over the substrate, and a pull-up transistor over the substrate. The pull-up transistor includes a first gate structure and first source/drain epitaxy structures on opposite sides of the first gate structure, in which each of the first source/drain epitaxy structures comprises a first epitaxy layer and a second epitaxy layer over the first epitaxy layer, wherein a germanium concentration of the first epitaxy layer is higher than a germanium concentration of the second epitaxy layer.Type: ApplicationFiled: April 3, 2023Publication date: August 3, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-I SHIH, Ren-Hua GUO
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Patent number: 11658032Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.Type: GrantFiled: March 18, 2021Date of Patent: May 23, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
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Patent number: 11621268Abstract: A method includes forming a first semiconductor fin over a p-well region of a substrate; forming a second semiconductor fin over an n-well region of a substrate; forming a gate structure crossing the first semiconductor fin and the second semiconductor fin; performing an implantation process to form a source/drain doped region in the first semiconductor fin; etching the second semiconductor fin to form a recess therein; performing a first epitaxy process to grow a first epitaxy layer in the recess; performing a second epitaxy process to grow a second epitaxy layer over the first epitaxy process; etching the second epitaxy layer to round a corner of the second epitaxy layer; forming an interlayer dielectric (ILD) layer covering the first semiconductor fin and the second epitaxy layer, wherein no etching is performed to the first semiconductor fin after forming the gate structure and prior to forming the ILD layer.Type: GrantFiled: August 5, 2021Date of Patent: April 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-I Shih, Ren-Hua Guo
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Publication number: 20210366914Abstract: A method includes forming a first semiconductor fin over a p-well region of a substrate; forming a second semiconductor fin over an n-well region of a substrate; forming a gate structure crossing the first semiconductor fin and the second semiconductor fin; performing an implantation process to form a source/drain doped region in the first semiconductor fin; etching the second semiconductor fin to form a recess therein; performing a first epitaxy process to grow a first epitaxy layer in the recess; performing a second epitaxy process to grow a second epitaxy layer over the first epitaxy process; etching the second epitaxy layer to round a corner of the second epitaxy layer; forming an interlayer dielectric (ILD) layer covering the first semiconductor fin and the second epitaxy layer, wherein no etching is performed to the first semiconductor fin after forming the gate structure and prior to forming the ILD layer.Type: ApplicationFiled: August 5, 2021Publication date: November 25, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-I SHIH, Ren-Hua GUO
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Patent number: 11088150Abstract: A method includes forming a semiconductor fin over a substrate; forming a plurality of isolation structures adjacent to the semiconductor fin; etching the semiconductor fin to form a recess between the isolation structures; forming a first epitaxy layer in the recess; forming a second epitaxy layer over the first epitaxy layer; forming a third epitaxy layer over the second epitaxy layer, in which the first epitaxy layer has a higher germanium (Ge) concentration than the second and third epitaxy layers; etching the third epitaxy layer; and forming a dielectric layer in contact with the third epitaxy layer after etching the third epitaxy layer.Type: GrantFiled: January 28, 2019Date of Patent: August 10, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-I Shih, Ren-Hua Guo
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Publication number: 20210210350Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.Type: ApplicationFiled: March 18, 2021Publication date: July 8, 2021Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
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Patent number: 10957540Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.Type: GrantFiled: December 18, 2019Date of Patent: March 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
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Publication number: 20200243544Abstract: A method includes forming a semiconductor fin over a substrate; forming a plurality of isolation structures adjacent to the semiconductor fin; etching the semiconductor fin to form a recess between the isolation structures; forming a first epitaxy layer in the recess; forming a second epitaxy layer over the first epitaxy layer; forming a third epitaxy layer over the second epitaxy layer, in which the first epitaxy layer has a higher germanium (Ge) concentration than the second and third epitaxy layers; etching the third epitaxy layer; and forming a dielectric layer in contact with the third epitaxy layer after etching the third epitaxy layer.Type: ApplicationFiled: January 28, 2019Publication date: July 30, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-I SHIH, Ren-Hua GUO
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Publication number: 20200126793Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.Type: ApplicationFiled: December 18, 2019Publication date: April 23, 2020Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
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Patent number: 10522353Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.Type: GrantFiled: July 24, 2018Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
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Patent number: 10475643Abstract: A method for manufacturing a semiconductor device includes introducing a gas into a chamber from a showerhead. The chamber has a sidewall surrounding a pedestal. The temperature of the showerhead is increased. The showerhead is thermally connected to the sidewall of the chamber, and a temperature of the sidewall of the chamber is increased by increasing the temperature of the showerhead.Type: GrantFiled: January 22, 2018Date of Patent: November 12, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ren-Hua Guo, Ju-Ru Hsieh, Jen-Hao Yang
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Publication number: 20180350601Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.Type: ApplicationFiled: July 24, 2018Publication date: December 6, 2018Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
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Patent number: 10147609Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.Type: GrantFiled: March 31, 2017Date of Patent: December 4, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
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Publication number: 20180175196Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.Type: ApplicationFiled: March 31, 2017Publication date: June 21, 2018Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
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Publication number: 20180144932Abstract: A method for manufacturing a semiconductor device includes introducing a gas into a chamber from a showerhead. The chamber has a sidewall surrounding a pedestal. The temperature of the showerhead is increased. The showerhead is thermally connected to the sidewall of the chamber, and a temperature of the sidewall of the chamber is increased by increasing the temperature of the showerhead.Type: ApplicationFiled: January 22, 2018Publication date: May 24, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ren-Hua GUO, Ju-Ru HSIEH, Jen-Hao YANG
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Chemical vapor deposition apparatus and method for manufacturing semiconductor device using the same
Patent number: 9899210Abstract: A method for manufacturing a semiconductor device includes forming a transistor on a substrate. Precursor gases are provided from a showerhead of a chemical vapor deposition (CVD) apparatus to form a contact etch stop layer (CESL) to cover the transistor and the substrate. A temperature of the showerhead is controlled in a range of about 70° C. to about 100° C. to control a temperature of the precursor gases.Type: GrantFiled: October 20, 2015Date of Patent: February 20, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ren-Hua Guo, Ju-Ru Hsieh, Jen-Hao Yang -
CHEMICAL VAPOR DEPOSITION APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME
Publication number: 20170110318Abstract: A method for manufacturing a semiconductor device includes forming a transistor on a substrate. Precursor gases are provided from a showerhead of a chemical vapor deposition (CVD) apparatus to form a contact etch stop layer (CESL) to cover the transistor and the substrate. A temperature of the showerhead is controlled in a range of about 70° C. to about 100° C. to control a temperature of the precursor gases.Type: ApplicationFiled: October 20, 2015Publication date: April 20, 2017Inventors: Ren-Hua GUO, Ju-Ru HSIEH, Jen-Hao YANG