Abstract: A baking apparatus for priming a substrate is provided, which includes a chamber, a hot plate and a barrier element. The hot plate is in the chamber and configured to bake the substrate on the hot plate. The barrier element is in contact with a periphery of the substrate and the hot plate to prevent contamination on a lower surface of the substrate. Another baking apparatus for priming a substrate is also provided, which includes a chamber and a hot plate. The hot plate is in the chamber and in full contact with a lower surface of the substrate to prevent contamination thereon.

Abstract: A baking apparatus for priming a substrate is provided, which includes a chamber, a hot plate and a barrier element. The hot plate is in the chamber and configured to bake the substrate on the hot plate. The barrier element is in contact with a periphery of the substrate and the hot plate to prevent contamination on a lower surface of the substrate. Another baking apparatus for priming a substrate is also provided, which includes a chamber and a hot plate. The hot plate is in the chamber and in full contact with a lower surface of the substrate to prevent contamination thereon.

Abstract: This invention discloses a novel design to obtain a good coating uniformity and to reduce the volume of viscous materials when coating by spraying the viscous material on the wafer during the first time period at a first predetermined pressures; spraying the viscous material on the wafer at a second predetermined pressure in response to the end of the first time period, the second predetermined pressure being lower than the first predetermined pressure; and spraying the viscous material on the wafer during a second time period at a time-varying pressure, the time-varying pressure being increased from the second predetermined pressure to a third predetermined pressure during the second time period.

Abstract: Correction of overlay shift of an epitaxial silicon layer deposited on a semiconductor wafer, and of post-epitaxial silicon layers subsequently deposited, is disclosed. When an epitaxial silicon layer of a given thickness is deposited, the zero mark coordinates for the deposition are shifted relative to alignment marks on the wafer by a distance based on the thickness of the layer. The distance is preferably proportional to the thickness of the epi layer. This prevents overlay shift of the epi layer. For post-epitaxial silicon layers subsequently deposited, preferably except for the first post-epi layer, a clear out process is initially performed to maintain the alignment marks on the semiconductor wafer. In this way, overlay shift, or misalignment, of the post-epi layers is also prevented.

Abstract: This invention discloses a novel design to obtain a good coating uniformity and to reduce the volume of viscous materials when coating by spraying the viscous material on the wafer during the first time period at a first predetermined pressures; spraying the viscous material on the wafer at a second predetermined pressure in response to the end of the first time period, the second predetermined pressure being lower than the first predetermined pressure; and spraying the viscous material on the wafer during a second time period at a time-varying pressure, the time-varying pressure being increased from the second predetermined pressure to a third predetermined pressure during the second time period.

Abstract: Correction of overlay shift of an epitaxial silicon layer deposited on a semiconductor wafer, and of post-epitaxial silicon layers subsequently deposited, is disclosed. When an epitaxial silicon layer of a given thickness is deposited, the zero mark coordinates for the deposition are shifted relative to alignment marks on the wafer by a distance based on the thickness of the layer. The distance is preferably proportional to the thickness of the epi layer. This prevents overlay shift of the epi layer. For post-epitaxial silicon layers subsequently deposited, preferably except for the first post-epi layer, a clear out process is initially performed to maintain the alignment marks on the semiconductor wafer. In this way, overlay shift, or misalignment, of the post-epi layers is also prevented.

Abstract: A method is described for determining more accurate Cauchy coefficients for a constant-angle reflection-interference spectrometer (CARIS). This allows photoresist thicknesses for product wafers to be measured more accurately. The method for determining the Cauchy coefficients consists of coating monitor wafers with photoresist layers having various thicknesses formed by varying the spin speed during photoresist coating. The photoresist layers are then patterned using monochromatic radiation through a mask and developing photoresist. The monochromatic radiation has a dose sufficient to just clear the photoresist layers from the surface of the wafers during development. The linewidths of the photoresist are measured and plotted as a function of photoresist thickness to generate a critical dimension (CD) swing curve having an essentially sinusoidal shape that results from interference between the transmitted and reflected monochromatic radiation in the photoresist.