Abstract: An arrangement (2) to calibrate a capacitive sensor interface (1) includes a capacitive sensor (10) having a capacitance (cmem, cmemsp, cmemsm) and a charge storing circuit (20) having a changeable capacitance (cdum, cdump, cdumm). A test circuit (30) applies a test signal (vtst) to the capacitive sensor (10) and the charge storing circuit (20). An amplifier circuit (40) has a first input connection (E40a) coupled to the capacitive sensor (10) and a second input connection (E40b) coupled to the charge storing circuit (20). The amplifier circuit (40) provides an output signal (Vout) in dependence on a first input signal (?Verr1) applied to the first input connection (E40a) and a second input signal (?Verr2) applied to the second input connection (E40b). A control circuit (60) is configured to trim the capacitance (cdum, cdump, cdumm) of the charge storing circuit (20) such that the level of the output signal (Vout) tends to the level of zero.

Abstract: A MEMS sensor (1) comprises a MEMS transducer (10) being coupled to a MEMS interface circuit (20). The MEMS interface circuit (20) comprises a bias voltage generator (100), a differential amplifier (200), a capacitor (300) and a feedback control circuit (400). The bias voltage generator (100) generates a bias voltage (Vbias) for operating the MEMS transducer. The variable capacitor (300) is connected to one of the input nodes (I200a) of the differential amplifier (200). At least one of the output nodes (A200a, A200b) of the differential amplifier is coupled to a base terminal (T110) of an output filter (110) of the bias voltage generator (100). Any disturbing signal from the bias voltage generator (100) is a common-mode signal that is divided equally on the input nodes (I200a, I200b) of the differential amplifier (200) and is therefore rejected.

Abstract: An arrangement (2) to calibrate a capacitive sensor interface (1) comprises a capacitive sensor (10) having a capacitance (cmem, cmemsp, cmemsm) and a charge storing circuit (20) having a changeable capacitance (cdum, cdump, cdumm). A test circuit (30) applies a test signal (vtst) to the capacitive sensor (10) and the charge storing circuit (20). An amplifier circuit (40) has a first input connection (E40a) coupled to the capacitive sensor (10) and a second input connection (E40b) coupled to the charge storing circuit (20). The amplifier circuit (40) provides an output signal (Vout) in dependence on a first input signal (?Verr1) applied to the first input connection (E40a) and a second input signal (?Verr2) applied to the second input connection (E40b). A control circuit (60) is configured to trim the capacitance (cdum, cdump, cdumm) of the charge storing circuit (20) such that the level of the output signal (Vout) tends to the level of zero.

Abstract: An amplifier circuit (AC) for amplifying an output signal (OS) of a capacitive sensor (M) comprises a first input terminal (AIN) to receive the output signal (OS) of the capacitive sensor (M) and a second input terminal (BIN) to receive a bias voltage (Vbias) of the capacitive sensor (M). The amplifier circuit (AC) comprises an amplifier (A) for amplifying the output signal (OS) and a control circuit (CF) arranged in a feedback loop (FL) of the amplifier (A) being configured to control a DC voltage level at an input connection (A1) of the amplifier (A). A bias voltage sensing circuit (BVS) senses a change of the level of the bias voltage (Vbias) at the second input terminal (BIN) and changes the bandwidth of the feedback loop (FL) in dependence on the sensed change of the level of the bias voltage (Vbias).

Abstract: A MEMS sensor (1) comprises a MEMS transducer (10) being coupled to a MEMS interface circuit (20). The MEMS interface circuit (20) comprises a bias voltage generator (100), a differential amplifier (200), a capacitor (300) and a feedback control circuit (400). The bias voltage generator (100) generates a bias voltage (Vbias) for operating the MEMS transducer. The variable capacitor (300) is connected to one of the input nodes (I200a) of the differential amplifier (200). At least one of the output nodes (A200a, A200b) of the differential amplifier is coupled to a base terminal (T110) of an output filter (110) of the bias voltage generator (100). Any disturbing signal from the bias voltage generator (100) is a common-mode signal that is divided equally on the input nodes (I200a, I200b) of the differential amplifier (200) and is therefore rejected.