Patents by Inventor Ren-Song Tsay

Ren-Song Tsay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10192019
    Abstract: A computer implemented method for routing a first path in a circuit design is presented. The method includes iteratively building a multitude of partial-paths to route the first path by adding an incremental length to a selected previously built partial-path when the computer is invoked to route the first path in the circuit design, the adding being performed in accordance with at least a first design rule. The multitude of partial-paths start at a first location. The method further includes comparing each of the multitude of partial-paths to each other when the multitude of partial-paths end on a common second location different from the first location, and saving one of the multitude of partial-paths that leads to a shortest first path. The method further includes eliminating one of the multitude of partial-paths that are not selected to lead to the shortest first path.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: January 29, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak
  • Patent number: 9665679
    Abstract: A computer implemented method for designing an integrated circuit (IC) having dimensions along first and second directions, and comprising at least a first block is presented. The method includes evaluating a demand ratio for the first block, the demand ratio being reflective of a ratio of a conductive wiring demand along the first direction and a conductive wiring demand along the second direction, when the computer is invoked to evaluate the demand ratio for the first block. The method further includes creating one or more wiring reservation blocks in accordance with the demand ratio.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: May 30, 2017
    Assignee: Synopsys, Inc.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Patent number: 9195788
    Abstract: The present invention provides a method for efficient resource-oriented power evaluation. By mapping instructions to microarchitecture components, both advantages of high-level simulation performance and fine-grained power model are obtained. The present invention effectively reduces simulation runtime overhead and provides an accurate power estimation result. The present invention is nearly as accurate as gate-level simulators, with an error rate of less than 1.2 while achieving simulation speeds of up to 20 MIPS, five orders faster than a commercial gate-level simulator. By using the present invention, it is easy to analyze power consumption profile and peak power.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: November 24, 2015
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Tzu-Chi Huang, Ren-Song Tsay
  • Publication number: 20150089465
    Abstract: A computer implemented method for routing a first path in a circuit design is presented. The method includes iteratively building a multitude of partial-paths to route the first path by adding an incremental length to a selected previously built partial-path when the computer is invoked to route the first path in the circuit design, the adding being performed in accordance with at least a first design rule. The multitude of partial-paths start at a first location. The method further includes comparing each of the multitude of partial-paths to each other when the multitude of partial-paths end on a common second location different from the first location, and saving one of the multitude of partial-paths that leads to a shortest first path. The method further includes eliminating one of the multitude of partial-paths that are not selected to lead to the shortest first path.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 26, 2015
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak
  • Publication number: 20150046143
    Abstract: The present invention provides a method for efficient resource-oriented power evaluation. By mapping instructions to microarchitecture components, both advantages of high-level simulation performance and fine-grained power model are obtained. The present invention effectively reduces simulation runtime overhead and provides an accurate power estimation result. The present invention is nearly as accurate as gate-level simulators, with an error rate of less than 1.2 while achieving simulation speeds of up to 20 MIPS, five orders faster than a commercial gate-level simulator. By using the present invention, it is easy to analyze power consumption profile and peak power.
    Type: Application
    Filed: September 3, 2013
    Publication date: February 12, 2015
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Tzu-Chi Huang, Ren-Song Tsay
  • Publication number: 20150007123
    Abstract: A computer implemented method for designing an integrated circuit (IC) having dimensions along first and second directions, and comprising at least a first block is presented. The method includes evaluating a demand ratio for the first block, the demand ratio being reflective of a ratio of a conductive wiring demand along the first direction and a conductive wiring demand along the second direction, when the computer is invoked to evaluate the demand ration for the first block. The method further includes creating one or more wiring reservation blocks in accordance with the demand ratio.
    Type: Application
    Filed: September 15, 2014
    Publication date: January 1, 2015
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Patent number: 8875081
    Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: October 28, 2014
    Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Publication number: 20140068542
    Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.
    Type: Application
    Filed: February 26, 2013
    Publication date: March 6, 2014
    Applicants: SpringSoft USA, Inc, SpringSoft, Inc.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Patent number: 8549468
    Abstract: The present invention discloses a system for generating a software TLM model, comprising a processing unit; a compiler coupled to the processing unit to generate target binary codes of a target software; a decompiler coupled to the processing unit to decompile the target binary codes into high level codes, for example C or C++ codes, to generate a functional model of the target software, wherein the functional model includes a plurality of basic blocks; an execution time calculating module coupled to the processing unit to calculate overall execution time of the plurality of the basic blocks of the functional model; a sync point identifying module coupled to the processing unit to identify sync points of the software transaction-level modeling model; and a time annotating module coupled to the processing unit to annotate the overall execution time of the basic blocks and the sync points into the functional model to obtain the software transaction-level modeling model.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: October 1, 2013
    Assignee: National Tsing Hua University
    Inventors: Meng-Huan Wu, Ren-Song Tsay
  • Publication number: 20130179864
    Abstract: A deadlock free synchronization synthesizer for must-happen-before relations in at least two parallel programs or at least two threads each having multiple code segments has an input device to specify a synchronization point to involving code segments for each parallel program or thread and must-happen-before relations to the synchronization point, an analyzing module connected to the input device to detect existence of a deadlock in the parallel programs by using the must-happen-before relations, and a synthesizing module connected to the analyzing module to synthesize a practice code corresponding to the parallel programs if the deadlock existence detection is negative.
    Type: Application
    Filed: April 25, 2012
    Publication date: July 11, 2013
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Yi-Shan Lu, Hsien-Lun Pai, Meng-Huan Wu, Ren-Song Tsay
  • Patent number: 8423343
    Abstract: The present invention discloses a high-parallelism synchronization method for multi-core instruction-set simulation. The proposed method utilizes a new distributed scheduling mechanism for a parallel compiled MCISS. The proposed method can enhance the parallelism of the MCISS so that the computing power of a multi-core host machine can be effectively utilized. The distributed scheduling with the present invention's prediction method significantly shortens the waiting time which an ISS spends on synchronization.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: April 16, 2013
    Assignee: National Tsing Hua University
    Inventors: Meng-Huan Wu, Ren-Song Tsay
  • Patent number: 8407647
    Abstract: A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the “H/V Demand Ratio.” From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: March 26, 2013
    Assignees: Springsoft, Inc., Springsoft USA, Inc.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak
  • Publication number: 20130054854
    Abstract: The present invention presents an effective Cycle-count Accurate Transaction level (CCA-TLM) full bus modeling and simulation technique. Using the two-phase arbiter and master-slave models, an FSM-based Composite Master-Slave-pair and Arbiter Transaction (CMSAT) model is proposed for efficient and accurate dynamic simulations. This approach is particularly effective for bus architecture exploration and contention analysis of complex Multi-Processor System-on-Chip (MPSoC) designs.
    Type: Application
    Filed: February 16, 2012
    Publication date: February 28, 2013
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Mao-Lin Li, Chen-Kang Lo, Li-Chun Chen, Hong-Jie Huang, Jen-Chieh Yeh, Ren-Song Tsay
  • Patent number: 8352924
    Abstract: The present invention discloses a method for multi-core instruction-set simulation. The proposed method identifies the shared data segment and the dependency relationship between the different cores and thus effectively reduces the number of sync points and lowers the synchronization overhead, allowing multi-core instruction-set simulation to be performed more rapidly while ensuring that the simulation results are accurate. In addition, the present invention also discloses a device for multi-core instruction-set simulation.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: January 8, 2013
    Assignee: National Tsing Hua University
    Inventors: Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay
  • Patent number: 8336001
    Abstract: A method and apparatus for manufacturing an integrated circuit (IC), the method including, generating, by a graphical construction unit, a first graph corresponding to a first net of the IC, the first graph representing a pin of the first net as a vertex, and a connection between two pins of the first net as an edge, the first graph further corresponding to a first IC layout; identifying a first and a second pair of unconnected vertices in the first graph for inserting a first and a second redundant edge, respectively, the first redundant edge and the second redundant edge forming a first connected loop and a second connected loop, respectively, each loop further including at least two edges of the first graph; calculating a tolerance ratio for the first redundant edge and the second redundant edge; sorting the first and second redundant edge based on their tolerance ratio; calculating a yield rate change of the first IC layout associated with inserting one of the first or second redundant edge with a highest
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: December 18, 2012
    Assignee: Springsoft, Inc.
    Inventors: Fong-Yuan Chang, Wai-Kei Mak, Ren-Song Tsay
  • Publication number: 20120233410
    Abstract: The present invention discloses a shared-variable-based (SVB) approach for fast and accurate multi-core cache coherence simulation. While the intuitive, conventional approach, synchronizing at either every cycle or memory access, gives accurate simulation results, it has poor performance due to huge simulation overloads. In the present invention, timing synchronization is only needed before shared variable accesses in order to maintain accuracy while improving the efficiency in the proposed shared-variable-based approach.
    Type: Application
    Filed: March 13, 2011
    Publication date: September 13, 2012
    Applicant: National Tsing Hua University
    Inventors: Cheng-Yang FU, Meng-Huan Wu, Ren-Song Tsay
  • Publication number: 20120197625
    Abstract: In the present disclosure, the DOM approach for the simulation of OS preemptive scheduling has presented and demonstrated. By maintaining the data-dependency between the software tasks, and guaranteeing the order of shared variable accesses, it can accurately simulate the preemption effect. Moreover, the proposed DOM OS model is implemented to enable preemptive scheduling in SystemC.
    Type: Application
    Filed: January 28, 2011
    Publication date: August 2, 2012
    Applicant: National Tsing Hua University
    Inventors: Peng-Chih WANG, Meng-Huan Wu, Ren-Song Tsay
  • Publication number: 20120191441
    Abstract: The present invention discloses a high-parallelism synchronization method for multi-core instruction-set simulation. The proposed method utilizes a new distributed scheduling mechanism for a parallel compiled MCISS. The proposed method can enhance the parallelism of the MCISS so that the computing power of a multi-core host machine can be effectively utilized.
    Type: Application
    Filed: January 24, 2011
    Publication date: July 26, 2012
    Applicant: National Tsing Hua University
    Inventors: Meng-Huan Wu, Ren-Song Tsay
  • Publication number: 20120185231
    Abstract: The present invention discloses a cycle-count-accurate (CCA) processor modeling, which can achieve high simulation speeds while maintaining timing accuracy of the system simulation. The CCA processor modeling includes a pipeline subsystem model and a cache subsystem model with accurate cycle with accurate cycle count information and guarantees accurate timing and functional behaviors on processor interface. The CCA processor modeling further includes a branch predictor and a bus interface (BIF) to predict the branch of pipeline execution behavior (PEB) and to simulate the data accesses between the processor and the external components via an external bus, respectively. The experimental results show that the CCA processor modeling performs 50 times faster than the corresponding Cycle-accurate (CA) model while providing the same cycle count information as the target RTL model.
    Type: Application
    Filed: January 19, 2011
    Publication date: July 19, 2012
    Applicant: National Tsing Hua University
    Inventors: Chen-Kang LO, Li-Chun Chen, Meng-Huan Wu, Ren-Song Tsay
  • Publication number: 20110218791
    Abstract: The present invention provides a method for simulating processor power consumption, the method comprises: simulating a simulated processor; utilizing a power analysis model to analyze the simulated processor's execution of at least one fragment of a program, for generating power analysis of a plurality of basic blocks of the at least one fragment; computing at least one power correction factor between the plurality of basic block; utilizing a processing apparatus to generate a simulation model with power annotation based on the power analysis and the at least one power correction factor; and predicting power consumption of the simulated processor based on the simulation model with power annotation.
    Type: Application
    Filed: March 3, 2010
    Publication date: September 8, 2011
    Inventors: Chien-Min LEE, Chen-Kang Lo, Meng-Huan Wu, Ren-Song Tsay