Patents by Inventor Ren Sun
Ren Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11944679Abstract: A protocol has been developed for genetically engineering an attenuated pathogen such as the influenza virus that can grow in cells without interferons but has suppressed growth in cells with the interferons. The protocol comprises systematically identifying immune evasion functions on the pathogen's genome, then eliminating the immune evasion functions while maintaining a certain replication fitness of the pathogen. The resulting attenuated pathogen causes a strong immunologic response and can be used in a live attenuated vaccine.Type: GrantFiled: March 14, 2018Date of Patent: April 2, 2024Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Yushen Du, Nicholas C. Wu, Ren Sun
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Publication number: 20230416311Abstract: Provided herein are compositions related to vaccines, e.g., influenza vaccines, including, peptide based vaccines, nucleic acid based vaccines, recombinant virus based vaccines, antibody based vaccines, and virus based vaccines. Also provided herein are methods related to vaccines, e.g.Type: ApplicationFiled: June 30, 2023Publication date: December 28, 2023Inventors: Arthur YOUNG, Ren SUN, Nicholas C. WU
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Publication number: 20230305004Abstract: In various embodiments methods to improve the detection of a lateral-flow immunoassay for the sensitive detection of the SARS-CoV-2 nucleocapsid protein or other analytes, as well as devices that incorporate those methods are provided.Type: ApplicationFiled: August 16, 2021Publication date: September 28, 2023Applicant: The Regents of the University of CaliforniaInventors: Daniel Takashi Kamei, Daniel William Bradbury, Ren Sun, Yushen Du, Benjamin Ming Wu, Jasmine Thanh Trinh, Milo Ryan, Cassandra Marie Cantu
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Patent number: 11739127Abstract: Provided herein are compositions related to vaccines, e.g., influenza vaccines, including, peptide based vaccines, nucleic acid based vaccines, recombinant virus based vaccines, antibody based vaccines, and virus based vaccines. Also provided herein are methods related to vaccines, e.g., influenza vaccines, including methods of identifying epitopes for the vaccines, producing, formulating, and administering the vaccines.Type: GrantFiled: July 14, 2021Date of Patent: August 29, 2023Assignee: InvVax, Inc.Inventors: Arthur Young, Ren Sun, Nicholas C. Wu
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Publication number: 20220213504Abstract: Disclosed herein are Zika virus constructs and methods of using Zika virus constructs and Zika viruses to treat subjects in need thereof.Type: ApplicationFiled: May 20, 2020Publication date: July 7, 2022Inventors: Vaithilingaraja Arumugaswami, Gustavo Garcia, JR., David A. Nathanson, Ren Sun
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Patent number: 11329160Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top fin surface, an upper fin side surface portion adjacent to the top fin surface, and a lower fin side surface contiguously connected to the upper fin side surface portion. The lining oxide layer peripherally encloses the lower fin side surface portion of the semiconductor fin. The silicon nitride based layer is disposed conformally over the lining oxide layer. The gate oxide layer is disposed conformally over the top fin surface and the upper fin side surface portion.Type: GrantFiled: February 16, 2017Date of Patent: May 10, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Ta Wu, Shiu-Ko Jangjian, Chung-Ren Sun, Ming-Te Chen, Ting-Chun Wang, Jun-Jie Cheng
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Publication number: 20220002352Abstract: Provided herein are compositions related to vaccines, e.g., influenza vaccines, including, peptide based vaccines, nucleic acid based vaccines, recombinant virus based vaccines, antibody based vaccines, and virus based vaccines. Also provided herein are methods related to vaccines, e.g., influenza vaccines, including methods of identifying epitopes for the vaccines, producing, formulating, and administering the vaccines.Type: ApplicationFiled: July 14, 2021Publication date: January 6, 2022Inventors: Arthur YOUNG, Ren SUN, Nicholas C. WU
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Patent number: 11111277Abstract: Provided herein are compositions related to vaccines, e.g., influenza vaccines, including, peptide based vaccines, nucleic acid based vaccines, recombinant virus based vaccines, antibody based vaccines, and virus based vaccines. Also provided herein are methods related to vaccines, e.g., influenza vaccines, including methods of identifying epitopes for the vaccines, producing, formulating, and administering the vaccines.Type: GrantFiled: December 28, 2017Date of Patent: September 7, 2021Assignees: InvVax, Inc., The Regents of the University of CaliforniaInventors: Arthur Young, Ren Sun, Nicholas C. Wu
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Patent number: 11004973Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.Type: GrantFiled: June 3, 2019Date of Patent: May 11, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chung-Ren Sun, Shiu-Ko Jangjian, Kun-Ei Chen, Chun-Che Lin
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Publication number: 20200129612Abstract: A protocol has been developed for genetically engineering an attenuated pathogen such as the influenza virus that can grow in cells without interferons but has suppressed growth in cells with the interferons. The protocol comprises systematically identifying immune evasion functions on the pathogen's genome, then eliminating the immune evasion functions while maintaining a certain replication fitness of the pathogen. The resulting attenuated pathogen causes a strong immunologic response and can be used in a live attenuated vaccine.Type: ApplicationFiled: March 14, 2018Publication date: April 30, 2020Applicant: The Regents of the University of CaliforniaInventors: Yushen Du, Nicholas C. Wu, Ren Sun
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Publication number: 20190288110Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.Type: ApplicationFiled: June 3, 2019Publication date: September 19, 2019Inventors: Chung-Ren SUN, Shiu-Ko JANGJIAN, Kun-Ei CHEN, Chun-Che LIN
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Patent number: 10312366Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.Type: GrantFiled: July 28, 2017Date of Patent: June 4, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Ren Sun, Shiu-Ko Jangjian, Kun-Ei Chen, Chun-Che Lin
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Publication number: 20170345928Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.Type: ApplicationFiled: July 28, 2017Publication date: November 30, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Ren SUN, Shiu-Ko JANGJIAN, Kun-Ei CHEN, Chun-Che LIN
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Patent number: 9722076Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions disposed in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.Type: GrantFiled: August 29, 2015Date of Patent: August 1, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURNING CO., LTD.Inventors: Chung-Ren Sun, Shiu-Ko Jangjian, Kun-Ei Chen, Chun-Che Lin
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Publication number: 20170162395Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top fin surface, an upper fin side surface portion adjacent to the top fin surface, and a lower fin side surface contiguously connected to the upper fin side surface portion. The lining oxide layer peripherally encloses the lower fin side surface portion of the semiconductor fin. The silicon nitride based layer is disposed conformally over the lining oxide layer. The gate oxide layer is disposed conformally over the top fin surface and the upper fin side surface portion.Type: ApplicationFiled: February 16, 2017Publication date: June 8, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Ta WU, Shiu-Ko JANGJIAN, Chung-Ren SUN, Ming-Te CHEN, Ting-Chun WANG, Jun-Jie CHENG
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Patent number: 9589804Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface. The lining oxide layer peripherally encloses the second side surface of the semiconductor fin. The silicon nitride based layer is disposed conformal to the lining oxide layer. The gate oxide layer is disposed conformal to the top surface and the first side surface.Type: GrantFiled: July 30, 2015Date of Patent: March 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Ta Wu, Shiu-Ko Jangjian, Chung-Ren Sun, Ming-Te Chen, Ting-Chun Wang, Jun-Jie Cheng
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Publication number: 20170062612Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions disposed in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.Type: ApplicationFiled: August 29, 2015Publication date: March 2, 2017Inventors: Chung-Ren SUN, Shiu-Ko JANGJIAN, Kun-Ei CHEN, Chun-Che LIN
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Patent number: 9570557Abstract: Techniques in fabricating a fin field-effect transistor (FinFET) include providing a substrate having a fin structure and forming an isolation region having a top surface with a first surface profile. A dopant species is implanted using a tilt angle to edge portions of the top surface. The edge portions are then removed using an etch process. In this respect, the isolation region is modified to have a second surface profile based on an etching rate that is greater than an etching rate used at other portions of the top surface. The second surface profile has a step height that is smaller than a step height corresponding to the first surface profile. The tilt implantation and etching process can be performed before a gate structure is formed, after the gate structure is formed but before the fin structure is recessed, or after the fin structure is recessed.Type: GrantFiled: April 29, 2015Date of Patent: February 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen Cheng Chou, Chung-Ren Sun, Chii-Ming Wu, Cheng-Ta Wu, Tzu kai Lin
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Publication number: 20170032970Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface. The lining oxide layer peripherally encloses the second side surface of the semiconductor fin. The silicon nitride based layer is disposed conformal to the lining oxide layer. The gate oxide layer is disposed conformal to the top surface and the first side surface.Type: ApplicationFiled: July 30, 2015Publication date: February 2, 2017Inventors: Cheng-Ta WU, Shiu-Ko JANGJIAN, Chung-Ren SUN, Ming-Te CHEN, Ting-Chun WANG, Jun-Jie CHENG
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Publication number: 20160326482Abstract: A system includes a processor and a memory storing processor-executable instructions, which when executed by the processor direct the processor to provide control data indicating application of a stimulus to a biological system, obtain sensor data indicating measurements of a response of the biological system to the stimulus, determine fitting parameters of a biological system model based on the response of the biological system to the stimulus, and predict a magnitude of the stimulus that, when applied to the biological system, will yield an optimized response of the biological system based on the model.Type: ApplicationFiled: July 20, 2016Publication date: November 10, 2016Inventors: Chih-Ming HO, Pak Kin WONG, Ren SUN, Fuqu YU