Abstract: A hybrid loop filter includes an integrator having an input and an output wherein the output forms an output of the hybrid loop filter, a plurality of transconductance amplifiers having an input and an output wherein each output of the plurality of transconductance amplifiers is coupled to the input of the integrator, a switched capacitor low pass chain having an input and a plurality of branches wherein each of the plurality of branches is coupled to the input of a separate one of said plurality of transconductance amplifiers, and a feedthrough branch having an input and an output wherein the input is coupled to the input of the switched capacitor low pass chain to form an input of said hybrid loop filter, and the output is coupled to the input of a separate one of the plurality of transconductance amplifiers.

Abstract: A hybrid loop filter includes an integrator having an input and an output wherein the output forms an output of the hybrid loop filter, a plurality of transconductance amplifiers having an input and an output wherein each output of the plurality of transconductance amplifiers is coupled to the input of the integrator, a switched capacitor low pass chain having an input and a plurality of branches wherein each of the plurality of branches is coupled to the input of a separate one of said plurality of transconductance amplifiers, and a feedthrough branch having an input and an output wherein the input is coupled to the input of the switched capacitor low pass chain to form an input of said hybrid loop filter, and the output is coupled to the input of a separate one of the plurality of transconductance amplifiers.

Abstract: A decimation filter includes a zero insertion filter having an input and an output, wherein the input forms an input of the decimation filter; a cascade of four comb filters having a first accumulator stage and a second stage having a first differentiator portion and second differentiator portion wherein the first stage has an input coupled to the output of the zero insertion filter and an output, the first differentiator portion has an input coupled to the output of the first stage and an output, and the second differentiator portion has an input coupled to the output of the first differentiator portion and an output, and a frequency shaping filter having an input and an output, wherein the input is coupled to the output of the second differentiator portion and the output forms an output of the decimation filter.

Abstract: A hybrid loop filter includes an integrator having an input and an output wherein the output forms an output of the hybrid loop filter, a plurality of transconductance amplifiers having an input and an output wherein each output of the plurality of transconductance amplifiers is coupled to the input of the integrator, a switched capacitor low pass chain having an input and a plurality of branches wherein each of the plurality of branches is coupled to the input of a separate one of said plurality of transconductance amplifiers, and a feedthrough branch having an input and an output wherein the input is coupled to the input of the switched capacitor low pass chain to form an input of said hybrid loop filter, and the output is coupled to the input of a separate one of the plurality of transconductance amplifiers.

Abstract: A hybrid loop filter includes an integrator having an input and an output wherein the output forms an output of the hybrid loop filter, a plurality of transconductance amplifiers having an input and an output wherein each output of the plurality of transconductance amplifiers is coupled to the input of the integrator, a switched capacitor low pass chain having an input and a plurality of branches wherein each of the plurality of branches is coupled to the input of a separate one of said plurality of transconductance amplifiers, and a feedthrough branch having an input and an output wherein the input is coupled to the input of the switched capacitor low pass chain to form an input of said hybrid loop filter, and the output is coupled to the input of a separate one of the plurality of transconductance amplifiers.

Abstract: A digital-to-analog converter (DAC) includes a first array of current source cells extending in first and second transverse directions, and a two-dimensional symmetrical controller for operating current source cells of the first array based upon at least a portion of digital input words and in a symmetrical sequence in both the first and second directions with respect to a medial position of the first array. The medial position preferably defines a centroid for the first array. The two-dimensional symmetrical controller may preferably include a decoder for generating a plurality of control signals based upon predetermined most significant bits (MSBs) of digital input words. Another aspect of the invention relates to the treatment of the LSBs. According to this aspect, the first array further comprises a plurality of second current source cells, and the two-dimensional symmetrical controller further operates the plurality of second current source cells based upon predetermined LSBs of digital input words.