Patents by Inventor Renan LETHIECQ
Renan LETHIECQ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11920989Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.Type: GrantFiled: March 4, 2021Date of Patent: March 5, 2024Assignee: STMicroelectronics SAInventors: Philippe Galy, Renan Lethiecq
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Patent number: 11867570Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal imposes the drain-source current of the first transistor.Type: GrantFiled: March 4, 2021Date of Patent: January 9, 2024Assignee: STMicroelectronics SAInventors: Philippe Galy, Renan Lethiecq
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Publication number: 20210278288Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.Type: ApplicationFiled: March 4, 2021Publication date: September 9, 2021Applicant: STMicroelectronics SAInventors: Philippe GALY, Renan LETHIECQ
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Publication number: 20210278287Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.Type: ApplicationFiled: March 4, 2021Publication date: September 9, 2021Applicant: STMicroelectronics SAInventors: Philippe GALY, Renan LETHIECQ
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Publication number: 20210278286Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.Type: ApplicationFiled: March 4, 2021Publication date: September 9, 2021Applicant: STMicroelectronics SAInventors: Philippe GALY, Renan LETHIECQ
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Patent number: 11037938Abstract: An exemplary semiconductor memory includes a channel region disposed in a semiconductor body, a gate region overlying the channel region, a first and a second source/drain region disposed in the semiconductor body, where the first source/drain region is spaced from the second source/drain region by the channel region. The exemplary memory further includes a first contact electrically contacting the first source/drain region, a second contact electrically contacting the first source/drain region and spaced from the second contact, and a third contact electrically contacting the second source/drain region. The first and second contacts are configured so that a resistivity of the first source/drain region can be irreversibly increased by application of an electric current between the first and second contacts. The first contact extends over a first width, the third contact extends over a third width, where the first width is smaller than the third width.Type: GrantFiled: October 7, 2019Date of Patent: June 15, 2021Assignee: STMICROELECTRONICS S.A.Inventors: Philippe Galy, Renan Lethiecq
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Patent number: 10795396Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.Type: GrantFiled: September 16, 2019Date of Patent: October 6, 2020Assignee: STMicroelectronics SAInventors: Renan Lethiecq, Philippe Galy
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Patent number: 10659034Abstract: An integrated electronic device includes a silicon-on-insulator (SOI) substrate. At least one MOS transistor is formed in and on the SOI substrate. The at least one MOS transistor has a gate region receiving a control voltage, a back gate receiving an adjustment voltage, a source/drain region having a resistive portion, a first terminal coupled to a first voltage (e.g., a reference voltage) and formed in the source/drain region and on a first side of the resistive portion, and a second terminal generating a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source/drain region and on a second side of the resistive portion. Adjustment circuitry generates the adjustment voltage as having a value dependent on the control voltage and on the voltage generated by the second terminal.Type: GrantFiled: June 3, 2019Date of Patent: May 19, 2020Assignee: STMicroelectronics SAInventors: Philippe Galy, Renan Lethiecq
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Publication number: 20200119024Abstract: A method can be used to irreversibly program a memory cell that includes a MOS transistor having a first source/drain region and a second source/drain region separated by a channel region that is adjacent a gate region. The method includes applying an electric current along a width of the first source/drain region to cause a resistivity of the first source/drain region to be irreversibly increased.Type: ApplicationFiled: October 7, 2019Publication date: April 16, 2020Inventors: Philippe Galy, Renan Lethiecq
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Publication number: 20200097036Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.Type: ApplicationFiled: September 16, 2019Publication date: March 26, 2020Applicant: STMicroelectronics SAInventors: Renan LETHIECQ, Philippe GALY
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Publication number: 20190372568Abstract: An integrated electronic device includes a silicon-on-insulator (SOI) substrate. At least one MOS transistor is formed in and on the SOI substrate. The at least one MOS transistor has a gate region receiving a control voltage, a back gate receiving an adjustment voltage, a source/drain region having a resistive portion, a first terminal coupled to a first voltage (e.g., a reference voltage) and formed in the source/drain region and on a first side of the resistive portion, and a second terminal generating a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source/drain region and on a second side of the resistive portion. Adjustment circuitry generates the adjustment voltage as having a value dependent on the control voltage and on the voltage generated by the second terminal.Type: ApplicationFiled: June 3, 2019Publication date: December 5, 2019Applicant: STMicroelectronics SAInventors: Philippe GALY, Renan LETHIECQ