Abstract: A hybrid switch for a power converter and a method of operating said hybrid switch, the hybrid switch comprising: at a minimum a first and a second element comprising one or more switching devices of a first semiconductor type, and at a minimum a third element comprising one or more switching devices of a second semiconductor type, wherein the second semiconductor type is different from the first semiconductor type, and wherein each element is independently configurable and connected to a separate respective control terminal; and, a controller connected to the control terminals, wherein the controller is configured to control each element independently through each respective control terminal, and wherein the controller is further configured to activate elements based on a measured or estimated current and/or power as required by an operating condition of the converter.

Abstract: A power semiconductor device includes a semiconductor wafer having a first main side surface and a second main side surface. The semiconductor wafer includes a first semiconductor layer having a first conductivity type and a plurality of columnar or plate-shaped first semiconductor regions extending in the first semiconductor layer between the first main side surface and the second main side surface in a vertical direction perpendicular to the first main side surface and the second main side surface. The first semiconductor regions have a second conductivity type, which is different from the first conductivity type. Therein, the first semiconductor is a layer of hexagonal silicon carbide. The first semiconductor regions are regions of 3C polytype silicon carbide.

Abstract: An embodiment provides a power semiconductor device having a low on-state resistance while avoiding any short channel effects and having a low subthreshold slope. The embodiment provides a trench power semiconductor device, which comprises a compensation layer of a first conductivity type, wherein the compensation layer is extending on a gate insulation layer between a source layer of the first conductivity type and a substrate layer of the first conductivity type directly adjacent to a channel region of a second conductivity type.

Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) forming source regions by applying a first mask with a first and second mask layer and applying an n dopant, forming a well layer by removing such part of the first mask, which is arranged between the two source regions, and applying a p dopant, forming two channel regions by forming a third mask by performing an etching step, by which the first mask layer is farther removed at the openings than the second mask layer, and then removing the second mask layer, wherein the remaining first mask layer forms a third mask and applying a p dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers.

Abstract: A power semiconductor device includes a semiconductor wafer having a first main side surface and a second main side surface. The semiconductor wafer includes a first semiconductor layer having a first conductivity type and a plurality of columnar or plate-shaped first semiconductor regions extending in the first semiconductor layer between the first main side surface and the second main side surface in a vertical direction perpendicular to the first main side surface and the second main side surface. The first semiconductor regions have a second conductivity type, which is different from the first conductivity type. Therein, the first semiconductor is a layer of hexagonal silicon carbide. The first semiconductor regions are regions of 3C polytype silicon carbide.

Abstract: A wide bandgap semiconductor device is comprising an (n?) doped drift layer between a first main side and a second main side. On the first main side, n doped source regions are arranged which are laterally surrounded by p doped channel layers having a channel layer depth. P+ doped well layers having a well layer depth, which is at least as large as the channel layer depth is arranged at the bottom of the source regions. A p++ doped plug extends from a depth, which is at least as deep as the source layer depth and less deep than the well layer depth, to a plug depth, which is as least as deep as the well layer depth, and having a higher doping concentration than the well layers, is arranged between the source regions and well layers. On the first main side, an ohmic contact contacts as a first main electrode the source regions, the well layers and the plug.

Abstract: The power semiconductor device according to the invention is a trench power field effect transistor, at all locations within a channel region a first local doping concentration is less than 1·1017 cm?3. In the base layer a second local doping concentration is at least 1·1017 cm?3 at all locations within the base layer. In the invention a channel length LCH, fulfils the following inequation: L CH > 4 ? ? ( ( ? CH ? t CH ? t GI ) ? GI ) , wherein ?CH is a permittivity of the channel region, ?GI is a permittivity of the gate insulation layer, tCH is a thickness of the channel region in a direction perpendicular to an interface between the gate insulation layer and the channel region, and tGI is a thickness of the gate insulation layer in a direction perpendicular to the interface between the gate insulation layer and the channel region.

Abstract: A power semiconductor device includes a plurality of vertical field effect transistor cells arranged in a plurality of parallel rows, each row including vertical field effect transistor cells arranged along a first direction, wherein in each vertical field effect transistor cell a body region is surrounded by the gate layer from two lateral surfaces of the body region opposite to each other. In each row of vertical field effect transistor cells the body regions are separated from each other in the first direction by first gate regions of the gate layer, each first gate region penetrating through the body layer, so that in each row of vertical field effect transistor cells the first gate regions alternate with the body regions along the first direction. The first gate regions within each row of vertical field effect transistor cells are connected with each other by second gate regions extending across the body regions of the respective vertical field effect transistor cells in the first direction.

Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) for forming two channel layers applying a first mask and applying a p first dopant, for forming two source regions forming a second mask by applying a further layer on the lateral sides of the first mask and applying an n second dopant, for forming two well layers forming a third mask by removing such part of the second mask between the source regions and applying a p third dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers; wherein the well layers surround the plug in the lateral direction and separate it from the two source regions.

Abstract: The present application provides a power semiconductor device having a low on-state resistance while avoiding any short channel effects and having a low subthreshold slope. To attain this object the invention provides a trench power semiconductor device, which includes a compensation layer of a first conductivity type, wherein the compensation layer is extending on a gate insulation layer between a source layer of the first conductivity type and a substrate layer of the first conductivity type directly adjacent to a channel region of a second conductivity type, and wherein: L ch > 4 ? ? ( ? CR ? t COMP ? t GI ? GI ) . In the above inequation Lch is a channel length, ?CR is a permittivity of the channel region, ?GI is a permittivity of the gate insulation layer, tCOMP is a thickness of the compensation layer and tGI is a thickness of the gate insulation layer.

Abstract: A semiconductor power rectifier with increased surge current capability is described. A semiconductor layer includes a drift layer having a first conductivity type, at least one pilot region having a second conductivity type different from the first conductivity type, a plurality of stripe-shaped emitter regions having the second conductivity type, and a transition region having the second conductivity type, wherein the at least one pilot region has in any lateral direction parallel to the first main side a width of at least 200 ?m and is formed adjacent to the first main side to form a first p-n junction with the drift layer, each emitter region is formed adjacent to the first main side form a second p-n junction with the drift layer, and the transition region is formed adjacent to the first main side to form a third p-n junction with the drift layer.

Abstract: A wide bandgap semiconductor device is comprising an (n?) doped drift layer between a first main side and a second main side. On the first main side, n doped source regions are arranged which are laterally surrounded by p doped channel layers having a channel layer depth. P+ doped well layers having a well layer depth, which is at least as large as the channel layer depth is arranged at the bottom of the source regions. A p++ doped plug extends from a depth, which is at least as deep as the source layer depth and less deep than the well layer depth, to a plug depth, which is as least as deep as the well layer depth, and having a higher doping concentration than the well layers, is arranged between the source regions and well layers. On the first main side, an ohmic contact contacts as a first main electrode the source regions, the well layers and the plug.

Abstract: A power semiconductor device includes a plurality of vertical field effect transistor cells arranged in a plurality of parallel rows, each row including vertical field effect transistor cells arranged along a first direction, wherein in each vertical field effect transistor cell a body region is surrounded by the gate layer from two lateral surfaces of the body region opposite to each other. In each row of vertical field effect transistor cells the body regions are separated from each other in the first direction by first gate regions of the gate layer, each first gate region penetrating through the body layer, so that in each row of vertical field effect transistor cells the first gate regions alternate with the body regions along the first direction. The first gate regions within each row of vertical field effect transistor cells are connected with each other by second gate regions extending across the body regions of the respective vertical field effect transistor cells in the first direction.

Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) forming source regions by applying a first mask with a first and second mask layer and applying an n dopant, forming a well layer by removing such part of the first mask, which is arranged between the two source regions, and applying a p dopant, forming two channel regions by forming a third mask by performing an etching step, by which the first mask layer is farther removed at the openings than the second mask layer, and then removing the second mask layer, wherein the remaining first mask layer forms a third mask and applying a p dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers.

Abstract: It is the object of the invention to provide a power semiconductor rectifier with a low on-state-voltage and high blocking capability. The object is attained by a power semiconductor rectifier comprising: a drift layer having a first conductivity type; and an electrode layer forming a Schottky contact with the drift layer, wherein the drift layer includes a base layer having a peak net doping concentration, below 1·1016 cm?3 and a barrier modulation layer which is in direct contact with the electrode layer to form at least a part of the Schottky contact, wherein a net doping concentration of the barrier modulation layer is in a range between 1·1016cm?3 and 1·1019 cm?3 and wherein the barrier modulation layer has a layer thickness in a direction vertical to the interface between the electrode layer and the barrier modulation, layer of at least 1 nm and less than 0.2 ?m.

Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) for forming two channel layers applying a first mask and applying a p first dopant, for forming two source regions forming a second mask by applying a further layer on the lateral sides of the first mask and applying an n second dopant, for forming two well layers forming a third mask by removing such part of the second mask between the source regions and applying a p third dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers; wherein the well layers surround the plug in the lateral direction and separate it from the two source regions.

Abstract: A semiconductor power rectifier with increased surge current capability is described, which has a semiconductor layer having a first main side and a second main side opposite to the first main side. The semiconductor layer includes a drift layer having a first conductivity type, at least one pilot region having a second conductivity type different from the first conductivity type, a plurality of stripe-shaped emitter regions having the second conductivity type, and a transition region having the second conductivity type, wherein the at least one pilot region has in any lateral direction parallel to the first main side a width of at least 200 ?m and is formed adjacent to the first main side to form a first p-n junction with the drift layer, each emitter region is formed adjacent to the first main side form a second p-n junction with the drift layer, and the transition region is formed adjacent to the first main side to form a third p-n junction with the drift layer.

Abstract: A method for manufacturing a wide bandgap junction barrier Schottky diode having an anode side and a cathode side is provided, wherein an (n+) doped cathode layer is arranged on the cathode side, at least on p doped anode layer is arranged on the anode side, an (n?) doped drift layer is arranged between the cathode layer and the at least one anode layer, which drift layer extends to the anode side, wherein the following manufacturing steps are performed: a) providing an (n+) doped wide bandgap substrate, b) creating the drift layer on the cathode layer, c) creating the at least one anode layer on the drift layer, d) applying a first metal layer on the anode side on top of the drift layer for forming a Schottky contact, characterized in, that e) creating a second metal layer on top of at least one anode layer, wherein after having created the first and the second metal layer, a metal layer on top of the at least one anode layer has a second thickness and a metal layer on top of the drift layer has a first thic

Abstract: A method for manufacturing a wide bandgap junction harrier Schottky diode (1) having an anode side (10) and a cathode side (15) is provided, wherein an (n±) doped cathode layer (2) is arranged on the cathode side (15), at least one p doped anode layer (3) is arranged on the anode side (10), an (n?) doped drift layer (4) is arranged between the cathode layer (2) and the at least one anode layer (3), which drift layer (4) extends to the anode side (10), wherein the following manufacturing steps are performed: a) providing an (n+) doped wide bandgap substrate(100), b) creating the drift layer (4) on the cathode layer (2), c) creating the at least one anode layer (3) on the drift layer (4), d) applying a first metal layer (5) on the anode side (10) on top of the drift layer (4) for forming a Schottky contact (55), characterized in, that e) creating a second metal layer (6) on top of at least one anode layer (3), wherein after having created the first and the second metal layer (5, 6), a metal layer on top of the

Abstract: It is the object of the invention to provide a power semiconductor rectifier with a low on-state voltage and high blocking capability. The object is attained by a power semiconductor rectifier comprising: a drift layer having a first conductivity type; and an electrode layer forming a Schottky contact with the drift layer, wherein the drift layer includes a base layer having a peak net doping concentration below 1-1016 cm?3 and a barrier modulation layer which is in direct contact with the electrode layer to form at least a part of the Schottky contact, wherein a net doping concentration of the barrier modulation layer is in a range between 1-1016 cm?3 and 1-1019 cm?3, and wherein the barrier modulation layer has a layer thickness in a direction vertical to the interface between the electrode layer and the barrier modulation layer of at least 1 nm and less than 0.2 ?m.