Abstract: A method of protecting a DRAM memory device from the row hammer effect, the memory device comprising a plurality of banks composed of memory rows, may be implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks. The prevention logic is also configured to execute a preventive refresh cycle of the sub-banks that is entirely executed before the number of rows activated in a sub-bank exceed a critical hammer value. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.

Abstract: A method of protecting a DRAM memory device from the row hammer effect, the memory device comprising a plurality of banks composed of memory rows, may be implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks. The prevention logic is also configured to execute a preventive refresh cycle of the sub-banks that is entirely executed before the number of rows activated in a sub-bank exceed a critical hammer value. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.

Abstract: A method of protecting a DRAM memory device from the row hammer effect includes the memory device comprising a plurality of banks composed of memory rows, the method being implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks and to execute, on each activation of a row of a sub-bank (b) of the memory, an increment step of a required number of preventive refreshments (REFRESH_ACC; REFRESH_ACC/PARAM_D) of the sub-bank (b) using an activation threshold (PARAM_D) of the sub-bank (b). The prevention logic is also configured to execute a preventive refresh sequence of the sub-banks according to their required number of preventive refreshes. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.

Abstract: A processor including multiple processing units for processing multiple elementary instructions in parallel, the elementary instructions including one or more syllables, each having a rank in the elementary instruction, and an input circuit configured to receive an instruction bundle including multiple elementary instructions, and to transmit to the processing units all syllables of first rank of the elementary instructions of the instruction bundle before syllables of second rank of the elementary instructions of the instruction bundle, the syllables of same rank being ordered according to the target processing unit of each syllable.

Abstract: A processor including multiple processing units for processing multiple elementary instructions in parallel, the elementary instructions including one or more syllables, each having a rank in the elementary instruction, and an input circuit configured to receive an instruction bundle including multiple elementary instructions, and to transmit to the processing units all syllables of first rank of the elementary instructions of the instruction bundle before syllables of second rank of the elementary instructions of the instruction bundle, the syllables of same rank being ordered according to the target processing unit of each syllable.

Abstract: The disclosure relates to a method for executing by a processor an instruction for saving/restoring several internal registers of the processor. The method comprises breaking down the saving/restoring instruction to generate micro-instructions for saving/restoring the content of a register, executing each of the micro-instructions, initializing a progress status of the saving/restoration of the registers, updating the progress status of the saving/restoration upon each generation of a micro-instruction for saving/restoring a register, saving the progress status in the event of an interruption in the saving/restoration of the registers to execute a higher-priority task, and restoring the progress status when the saving/restoration of the registers is resumed.

Abstract: The systems and methods disclosed relate to a processor comprising a processing unit and a debugging that which can be connected to an external emulator for debugging a program executed by the processor, the debugging interface including internal resources at least partially accessible to the external emulator. According to one embodiment, the debugging interface includes a selecting circuit for selecting an internal resource of the debugging interface, according to a reference supplied by the processing unit, and an access circuit that transfers a datum between the resource selected and a data field accessible by the processing unit.

Abstract: A method for debugging a multitask program executed by a processor includes interrupting the processor during the execution of a task of the program, and activating a debugging mode of the processor, wherein the instructions executed by the processor are supplied by an external emulator. The method comprises steps during which: the processor sends an activation message to the external emulator every time the debugging mode is activated, and upon receiving the activation message, the external emulator sends an acknowledgement message to the processor containing at least one portion of the activation message received.

Abstract: The disclosure relates to a method for executing by a processor an instruction for saving/restoring several internal registers of the processor. The method comprises breaking down the saving/restoring instruction to generate micro-instructions for saving/restoring the content of a register, executing each of the micro-instructions, initializing a progress status of the saving/restoration of the registers, updating the progress status of the saving/restoration upon each generation of a micro-instruction for saving/restoring a register, saving the progress status in the event of an interruption in the saving/restoration of the registers to execute a higher-priority task, and restoring the progress status when the saving/restoration of the registers is resumed.

Abstract: The systems and methods disclosed relate to a processor comprising a processing unit and a debugging interface which can be connected to an external emulator for debugging a program executed by the processor, the debugging interface comprising internal resources at least partially accessible to the external emulator. According to one embodiment, the debugging interface comprises a selecting circuit for selecting an internal resource of the debugging interface, according to a reference supplied by the processing unit, and access means for transferring a datum between the resource selected and a data field accessible by the processing unit.

Abstract: A method for debugging a multitask program executed by a processor includes interrupting the processor during the execution of a task of the program, and activating a debugging mode of the processor, wherein the instructions executed by the processor are supplied by an external emulator. The method comprises steps during which: the processor sends an activation message to the external emulator every time the debugging mode is activated, and upon receiving the activation message, the external emulator sends an acknowledgement message to the processor containing at least one portion of the activation message received.

Abstract: A method and device for detecting faults in an electronic circuit, such as a multiplexed latch includes n control inputs, p data inputs, and at least one output. The method involves trying to cause the electronic circuit to function to modify the state of the output with respect to a start state, knowing that if the state of the output effectively changes while the control inputs are inhibited, this means that at least one control input is stuck at logic 1.

Abstract: A method and device for collecting logic values output from a logic unit having n inputs and p outputs included within an electronic circuit is provided by p test cells. These test cells are connected in parallel respectively to the p outputs of the logic unit such that the logic values of the outputs of the logic unit are loaded into the test cells in a normal mode, and are connected in series with each other to form a shift register for propagating logic values of the outputs of the logic unit to a collecting node in a test mode. In a first phase, the logic values of one out of two outputs of the logic unit are propagated to the shift register. Then, in a second phase, the logic values of the other outputs of the logic unit are propagated in the shift register. The logic values of the outputs of the logic unit are reloaded in the test cells between the first and second phase.