Patents by Inventor Renaud Perez

Renaud Perez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7990759
    Abstract: The memory cell comprises first and second inverter circuits, connected in a loop. First and second decoupling transistors, normally turned off outside the write phases, are respectively connected between an output of the second inverter circuit and first and second inputs of the first inverter circuit. The memory cell is thereby protected against transient disturbances due to ionizing particles. The gates of the decoupling transistors are preferably respectively connected to a supply voltage for the P-type decoupling transistors and grounded for the N-type decoupling transistors.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: August 2, 2011
    Assignee: IROC Technologies
    Inventors: Michel Nicolaidis, Renaud Perez
  • Publication number: 20080253180
    Abstract: The memory cell comprises first and second inverter circuits, connected in a loop. First and second decoupling transistors, normally turned off outside the write phases, are respectively connected between an output of the second inverter circuit and first and second inputs of the first inverter circuit. The memory cell is thereby protected against transient disturbances due to ionizing particles. The gates of the decoupling transistors are preferably respectively connected to a supply voltage for the P-type decoupling transistors and grounded for the N-type decoupling transistors.
    Type: Application
    Filed: July 5, 2006
    Publication date: October 16, 2008
    Inventors: Michel Nicolaidis, Renaud Perez
  • Publication number: 20080077376
    Abstract: This application discloses a new, and useful computer implemented method and apparatus that can be used for the determination of SEU and SET disruptions in a cell or circuit, caused by ionizing particle strikes, including those caused by neutrons (cosmic rays), alpha particles or heavy ions. The method of the present invention includes a fast simulation tool (“TFIT”), which calculates the electrical effect of a particle's impact to a cell, or a circuit. The method is used to predict the soft error rate (SER) calculations and the FIT (number of failures-in-time) performance of designated test cell's design, depending on the type of particle environment specified. The method is designed to simulate the response of the cell or circuit to the stimuli caused by a particle strike. These stimuli are modeled as a “current source” placed between the drain and the source of each struck transistor.
    Type: Application
    Filed: May 29, 2007
    Publication date: March 27, 2008
    Applicant: iROC Technologies
    Inventors: Hafnaoui Belhaddad, Renaud Perez