Abstract: An architecture for processing a data stream forming matrices of pixels of dimension Nl×Nc. The processing architecture includes processing units and interconnection means making it possible to transfer the data stream between them. Each processing unit includes a control unit, neighborhood processors capable of carrying out the instructions from the control unit and a neighborhood storage unit enabling each neighborhood processor to access a neighborhood of dimension Vl×Vc. The invention makes it possible to extend the dimension of the neighborhoods accessible to the neighborhood processors by a coupling of two or more processing units. To this end, the architecture includes a storage manager enabling the neighborhood processors of the coupled processing units to access adjoining neighborhoods of pixels, and means for communication between neighborhood processors allowing for an exchange of data relating to the different neighborhoods.

Abstract: The invention provides a filtering device with hierarchical structure making it possible to carry out finite impulse response and infinite impulse response linear filtering functions and which can be combined with one or more devices of the same type. The device includes at least one first and one second filtering module having means for carrying out filtering functions with N configurable coefficients. A first subset of the N coefficients of a module is configured to carry out nonrecursive filtering functions, a second subset of the coefficients configured to carry out recursive filtering functions, one or more feedback loops able to be activated per module, at least one result sample of the filtering being generated at each clock cycle. The invention also provides a reconfigurable filtering device using at least two filtering devices with the hierarchical structure.

Abstract: The invention provides a reconfigurable module allowing morphological operations to be carried out for image processing. The module includes an operational block having five inputs, three outputs, three adders/subtracters and four logic blocks. The logic blocks provide various routings between the three adders/subtracters to enable the outputs to deliver the result of basic operations carried out on the five inputs. The reconfigurable module has a reduced number of components while at the same time allowing various morphological operations to be performed whose parameters can be modified. Furthermore, the reconfigurable module is serially combined to carry out more complex morphological operations. The invention also provides a method for implementing the reconfigurable module allowing an integral image, an eroded image, an expanded image, a distance image or projections along the rows and columns of the original image to be determined starting from an original image.

Abstract: An architecture for processing a data stream forming matrices of pixels of dimension Nl×Nc. The processing architecture includes processing units and interconnection means making it possible to transfer the data stream between them. Each processing unit includes a control unit, neighborhood processors capable of carrying out the instructions from the control unit and a neighborhood storage unit enabling each neighborhood processor to access a neighborhood of dimension Vl×Vc. The invention makes it possible to extend the dimension of the neighborhoods accessible to the neighborhood processors by a coupling of two or more processing units. To this end, the architecture includes a storage manager enabling the neighborhood processors of the coupled processing units to access adjoining neighborhoods of pixels, and means for communication between neighborhood processors allowing for an exchange of data relating to the different neighborhoods.

Abstract: The invention provides a filtering device with hierarchical structure making it possible to carry out finite impulse response and infinite impulse response linear filtering functions and which can be combined with one or more devices of the same type. The device includes at least one first and one second filtering module having means for carrying out filtering functions with N configurable coefficients. A first subset of the N coefficients of a module is configured to carry out nonrecursive filtering functions, a second subset of the coefficients configured to carry out recursive filtering functions, one or more feedback loops able to be activated per module, at least one result sample of the filtering being generated at each clock cycle. The invention also provides a reconfigurable filtering device using at least two filtering devices with the hierarchical structure.

Abstract: The invention provides a reconfigurable module allowing morphological operations to be carried out for image processing. The module includes an operational block having five inputs, three outputs, three adders/subtracters and four logic blocks. The logic blocks provide various routings between the three adders/subtracters to enable the outputs to deliver the result of basic operations carried out on the five inputs. The reconfigurable module has a reduced number of components while at the same time allowing various morphological operations to be performed whose parameters can be modified. Furthermore, the reconfigurable module is serially combined to carry out more complex morphological operations. The invention also provides a method for implementing the reconfigurable module allowing an integral image, an eroded image, an expanded image, a distance image or projections along the rows and columns of the original image to be determined starting from an original image.

Abstract: A multiprocessor system is disclosed wherein the processors communicate between each other asynchronously while carrying out synchronous processing. Each processor is associated with a cell connected to its neighbors by a ring network through which circulate messages for the processors. Each cell recognized the messages for its associated processor and communicates them to the associated processor. Particularly utility is found in the area of processing image-related data.