Patents by Inventor Rene A. Lujan
Rene A. Lujan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080135891Abstract: A transistor device is formed on a flexible substrate such that device processing remains at a low temperature. A first gate dielectric layer is formed over gate metal by annodization, eliminating relatively high-temperature dielectric deposition processes and difficulties with in-process substrate deformation. A second gate dielectric layer may optionally be provided over the first in order to provide an improved dielectric/semiconductor interface. A high performance pixel, and process for producing same, may thus be provided on a flexible substrate.Type: ApplicationFiled: December 8, 2006Publication date: June 12, 2008Applicant: PALO ALTO RESEARCH CENTER, INCORPORATEDInventors: Ana Claudia Arias, Rene Lujan, Robert Street
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Patent number: 7384568Abstract: Susceptibility of darkfield etch masks (majority of the mask area is opaque) to pinhole defects, transferred pattern, non-uniformity, etc. due to ejector dropout or drop misdirection, and long duty cycles due to large-area coverage, when using digital lithography (or print patterning) is addressed by using a clear-field print pattern that is then coated with etch resist material. The printed clear field pattern is selectively removed to form an inverse pattern (darkfield) within the coated resist layer. Etching then removes selected portions of an underlying (e.g., encapsulation, conductive, etc.) layer. Removal of the mask produces a layer with large-area features with substantially reduced defects.Type: GrantFiled: March 31, 2006Date of Patent: June 10, 2008Assignee: Palo Alto Research Center IncorporatedInventors: William Wong, Scott Limb, Beverly Russo, Michael Chabinyc, Rene Lujan
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Publication number: 20080121884Abstract: A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.Type: ApplicationFiled: January 23, 2008Publication date: May 29, 2008Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: William S. Wong, Rene A. Lujan, Eugene M. Chow
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Patent number: 7365022Abstract: A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.Type: GrantFiled: January 20, 2006Date of Patent: April 29, 2008Assignee: Palo Alto Research Center IncorporatedInventors: William Wong, Scott Limb, Michael Chabinyc, Beverly Russo, Rene A. Lujan
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Patent number: 7344928Abstract: A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.Type: GrantFiled: July 28, 2005Date of Patent: March 18, 2008Assignee: Palo Alto Research Center IncorporatedInventors: William S. Wong, Rene A. Lujan, Eugene M. Chow
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Patent number: 7309563Abstract: A method for performing a liftoff operation involves printing a liftoff pattern using low-resolution patterning techniques to form fine feature patterns. The resulting feature size is defined by the spacing between printed patterns rather than the printed pattern size. By controlling the cross-sectional profile of the printed liftoff pattern, mask structures may be formed from the liftoff operation having beneficial etch-mask aperture profiles. For example, a multi-layer printed liftoff pattern can be used to create converging aperture profiles in a patterned layer. The patterned layer can then be used as an etch mask, where the converging aperture profiles result in desirable diverging etched features.Type: GrantFiled: December 19, 2003Date of Patent: December 18, 2007Assignee: Palo Alto Research Center IncorporatedInventors: Kateri E. Paul, William S. Wong, Steven E. Ready, René A. Lujan
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Publication number: 20070235410Abstract: Susceptibility of darkfield etch masks (majority of the mask area is opaque) to pinhole defects, transferred pattern, non-uniformity, etc. due to ejector dropout or drop misdirection, and long duty cycles due to large-area coverage, when using digital lithography (or print patterning) is addressed by using a clear-field print pattern that is then coated with etch resist material. The printed clear field pattern is selectively removed to form an inverse pattern (darkfield) within the coated resist layer. Etching then removes selected portions of an underlying (e.g., encapsulation, conductive, etc.) layer. Removal of the mask produces a layer with large-area features with substantially reduced defects.Type: ApplicationFiled: March 31, 2006Publication date: October 11, 2007Inventors: William Wong, Scott Limb, Beverly Russo, Michael Chabinyc, Rene Lujan
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Publication number: 20070172969Abstract: A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.Type: ApplicationFiled: January 20, 2006Publication date: July 26, 2007Inventors: William Wong, Scott Limb, Michael Chabinyc, Beverly Russo, Rene Lujan
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Publication number: 20070158644Abstract: A backplane circuit includes an array of organic thin-film transistors (OTFTs), each OTFT including a source contact, a drain contact, and an organic semiconductor region extending between the source and drain contacts. The drain contacts in each row are connected to an address line. The source and drain contacts and the address lines are fabricated using a multi-layer structure including a relatively thick base portion formed of a relatively inexpensive metal (e.g., aluminum or copper), and a relatively thin contact layer formed of a high work function, low oxidation metal (e.g., gold) that exhibits good electrical contact to the organic semiconductor, is formed opposite at least one external surface of the base, and is located at least partially in an interface region where the organic semiconductor contacts an underlying dielectric layer.Type: ApplicationFiled: December 21, 2005Publication date: July 12, 2007Applicant: Palo Alto Research Center IncorporatedInventors: Michael Chabinyc, Rene Lujan, Ana Arias, Jackson Ho
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Patent number: 7189589Abstract: A method of fabricating a semiconductor device is described. In this method, a starting substrate of sufficient thickness is selected that has the required defect density levels, which may result in an undesirable doping level. Then a semiconductor layer having a desired doping level is formed on the starting substrate. The resulting semiconductor layer has the required defect density and doping levels for the final product application. After active components, electrical conductors, and any other needed structures are formed on the semiconductor layer, the starting substrate is removed leaving a desired thickness of the semiconductor layer. In a VECSEL application, the active components can be a gain cavity, where the semiconductor layer has the necessary defect density and doping levels to maximize wall plug efficiency (WPE). In one embodiment, the doping of the semiconductor layer is not uniform. For example, a majority of the layer is doped at a low level and the remainder is doped at a much higher level.Type: GrantFiled: December 16, 2003Date of Patent: March 13, 2007Assignee: Novalux, Inc.Inventors: Glen Phillip Carey, Ian Jenks, Alan Lewis, René Lujan, Hailong Zhou, Jacy R. Titus, Gideon W. Yoffe, Mark A. Emanuel, Aram Mooradian
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Publication number: 20070026585Abstract: A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.Type: ApplicationFiled: July 28, 2005Publication date: February 1, 2007Inventors: William Wong, Rene Lujan, Eugene Chow
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Publication number: 20070020883Abstract: A patterned integrated circuit structure defining a gap or via is fabricated solely by digital printing and bulk processing. A sacrificial lift-off pattern is printed or otherwise formed over a substrate, and then covered by a blanket layer. A mask is then formed, e.g., by printing a wax pattern that covers a region of the blanket layer corresponding to the desired patterned structure, and overlaps the lift-off pattern. Exposed portions of the blanket layer are then removed, e.g., by wet etching. The printed mask and the lift-off pattern are then removed using a lift-off process that also removes any remaining portions of the blanket layer formed over the lift-off pattern. A thin-film transistor includes patterned source/drain structures that are self-aligned to an underlying gate structure by forming a photoresist lift-off pattern that is exposed and developed by a back-exposure process using the gate structure as a mask.Type: ApplicationFiled: July 18, 2005Publication date: January 25, 2007Applicant: Palo Alto Research Center IncorporatedInventors: Ana Arias, Rene Lujan, William Wong
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Publication number: 20060065909Abstract: Various exemplary embodiments of the systems and methods according to this invention provide for a method of producing a self-aligned thin film transistor, the transistor including a metal layer covering at least a portion of a doped layer, the doped layer covering at least a portion of a dielectric layer, a strain being created in the metal layer, the method includes etching an exposed portion of the doped layer to create a defect at an interface between the doped layer and the dielectric layer so as to initiate a delamination of the doped layer from the dielectric layer. The delamination of the doped layer from the dielectric layer is stopped when the defect propagates into an interface between the doped layer and the dielectric layer that has an adhesive energy that is greater than the strain of the metal layer.Type: ApplicationFiled: September 28, 2004Publication date: March 30, 2006Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: William Wong, Chinwen Shih, Rene Lujan, Eugene Chow
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Patent number: 7018877Abstract: Various exemplary embodiments of the systems and methods according to this invention provide for a method of producing a self-aligned thin film transistor, the transistor including a metal layer covering at least a portion of a doped layer, the doped layer covering at least a portion of a dielectric layer, a strain being created in the metal layer, the method includes etching an exposed portion of the doped layer to create a defect at an interface between the doped layer and the dielectric layer so as to initiate a delamination of the doped layer from the dielectric layer. The delamination of the doped layer from the dielectric layer is stopped when the defect propagates into an interface between the doped layer and the dielectric layer that has an adhesive energy that is greater than the strain of the metal layer.Type: GrantFiled: September 28, 2004Date of Patent: March 28, 2006Assignee: Palo Alto Research CenterInventors: William Wong, Chinwen Shih, Rene A. Lujan, Eugene Chow
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Publication number: 20050136358Abstract: A method for performing a liftoff operation involves printing a liftoff pattern using low-resolution patterning techniques to form fine feature patterns. The resulting feature size is defined by the spacing between printed patterns rather than the printed pattern size. By controlling the cross-sectional profile of the printed liftoff pattern, mask structures may be formed from the liftoff operation having beneficial etch-mask aperture profiles. For example, a multi-layer printed liftoff pattern can be used to create converging aperture profiles in a patterned layer. The patterned layer can then be used as an etch mask, where the converging aperture profiles result in desirable diverging etched features.Type: ApplicationFiled: December 19, 2003Publication date: June 23, 2005Inventors: Kateri Paul, William Wong, Steven Ready, Rene Lujan
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Publication number: 20050014349Abstract: A method of fabricating a semiconductor device is described. In this method, a starting substrate of sufficient thickness is selected that has the required defect density levels, which may result in an undesirable doping level. Then a semiconductor layer having a desired doping level is formed on the starting substrate. The resulting semiconductor layer has the required defect density and doping levels for the final product application. After active components, electrical conductors, and any other needed structures are formed on the semiconductor layer, the starting substrate is removed leaving a desired thickness of the semiconductor layer. In a VECSEL application, the active components can be a gain cavity, where the semiconductor layer has the necessary defect density and doping levels to maximize wall plug efficiency (WPE). In one embodiment, the doping of the semiconductor layer is not uniform. For example, a majority of the layer is doped at a low level and the remainder is doped at a much higher level.Type: ApplicationFiled: December 16, 2003Publication date: January 20, 2005Inventors: Glen Carey, Ian Jenks, Alan Lewis, Rene Lujan, Hailong Zhou
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Patent number: 6504175Abstract: Amorphous and polycrystalline silicon (hybrid) devices are formed close to one another employing laser crystallization and back side lithography processes. A mask (e.g., TiW) is used to protect the amorphous silicon device during laser crystallization. A patterned nitride layer is used to protect the amorphous silicon device during rehydrogenation of the polycrystalline silicon. An absorption film (e.g., amorphous silicon) is used to compensate for the different transparencies of amorphous and polycrystalline silicon during the back side lithography. Device spacing of between 2 and 50 micrometers may be obtained, while using materials and process steps otherwise compatible with existing hybrid device formation processes.Type: GrantFiled: April 28, 1998Date of Patent: January 7, 2003Assignee: Xerox CorporationInventors: Ping Mei, Rene A. Lujan
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Patent number: 6348693Abstract: An x-ray imager and method of fabricating an x-ray imager that provides protection to the sensor arrays and the barrier layer from the corrosive effects of the scintillating material. The x-ray imager includes a benzo-cyclo-butene layer between the barrier layer and the scintillating material. The benzo-cyclo-butene layer provides several advantages including low cost and application by spin coating or spray coating.Type: GrantFiled: September 16, 1999Date of Patent: February 19, 2002Assignee: Xerox CorporationInventors: Richard L. Weisfield, Rene Lujan, Charles T. Malone
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Patent number: 6140668Abstract: Amorphous and polycrystalline silicon (hybrid) devices are formed close to one another employing laser crystallization and back side lithography processes. A mask (e.g., TiW) is used to protect the amorphous silicon device during laser crystallization. A patterned nitride layer is used to protect the amorphous silicon device during rehydrogenation of the polycrystalline silicon. An absorption film (e.g., amorphous silicon) is used to compensate for the different transparencies of amorphous and polycrystalline silicon during the back side lithography. Device spacing of between 2 and 50 micrometers may be obtained, while using materials and process steps otherwise compatible with existing hybrid device formation processes.Type: GrantFiled: April 28, 1998Date of Patent: October 31, 2000Assignee: Xerox CorporationInventors: Ping Mei, Rene A. Lujan
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Patent number: 6107641Abstract: An improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser doping technique is applied to fabricate such transistors. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.Type: GrantFiled: September 10, 1997Date of Patent: August 22, 2000Assignee: Xerox CorporationInventors: Ping Mei, Rene A. Lujan, James B. Boyce, Christopher L. Chua, Michael G. Hack