Patents by Inventor Rene Catalin Palalau

Rene Catalin Palalau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9841975
    Abstract: A method is provided of performing register allocation for at least one program code module. The method includes constructing a restriction graph for program variables within at least one program instruction, and determining whether the constructed restriction graph is colorable. If it is determined that the constructed restriction graph is not colorable, then the method determines whether at least one alternative form of the at least one program instruction is available, and modifies the at least one program instruction to comprise an alternative form if it is determined that at least one alternative form is available.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: December 12, 2017
    Assignee: NXP USA, Inc.
    Inventors: Andreea Florina Nicolescu, Rene Catalin Palalau
  • Patent number: 9513922
    Abstract: A computer system for generating an optimized program code from a program code having a loop with an exit branch, wherein the computer system comprises a processing unit, wherein the processing unit is arranged to convert an exit instruction of the exit branch into a predicated exit instruction, wherein the processing unit is arranged to determine common dependencies within the loop, wherein the processing unit is arranged to generate modified dependencies by adding additional dependencies to the common dependencies, and wherein the processing unit is arranged to apply an algorithm that uses software pipelining for generating an optimized program code for the loop based on the modified dependencies.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: December 6, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Rene Catalin Palalau
  • Publication number: 20160224343
    Abstract: A method of performing register allocation for at least one program code module. The method comprises constructing a restriction graph for program variables within at least one program instruction, and determining whether the constructed restriction graph is colourable. The method further comprises, if it is determined that the constructed restriction graph is not colourable, determining whether at least one alternative form of the at least one program instruction is available, and modifying the at least one program instruction to comprise an alternative form if it is determined that at least one alternative form is available.
    Type: Application
    Filed: September 18, 2013
    Publication date: August 4, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Andreea Florina NICOLESCU, Rene Catalin PALALAU
  • Publication number: 20150067662
    Abstract: A computer system for generating an optimized program code from a program code having a loop with an exit branch, wherein the computer system comprises a processing unit, wherein the processing unit is arranged to convert an exit instruction of the exit branch into a predicated exit instruction, wherein the processing unit is arranged to determine common dependencies within the loop, wherein the processing unit is arranged to generate modified dependencies by adding additional dependencies to the common dependencies, and wherein the processing unit is arranged to apply an algorithm that uses software pipelining for generating an optimized program code for the loop based on the modified dependencies.
    Type: Application
    Filed: April 20, 2012
    Publication date: March 5, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Rene Catalin Palalau