Patents by Inventor Rene Celis-Cordova

Rene Celis-Cordova has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adiabatic flip-flop and memory cell design
    Patent number: 11488660
    Abstract: In a method computer storage element operation, first and second rising (or falling) clock edges are applied to first and second power inputs of the computer storage element having a transistor array between the first and second power inputs over time T1 whereupon a logic value applied to an input of the transistor array is stored therein. Thereafter, first and second falling (or rising) clock edges are applied to the first and second power inputs over time T2, whereupon part of an electrical charge or energy associated with the logic value stored in the transistor array is provided to circuitry that generates the first and/or second clock edge(s), wherein the value(s) of time T1 and/or time T2 is/are greater than a product of RC, where R is resistance associated with the computer storage element, and C is a load capacitance associated with the computer storage element.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: November 1, 2022
    Assignees: INDIANA INTEGRATED CIRCUITS, LLC, UNIVERSITY OF NOTRE DAME DU LAC
    Inventors: Gregory Snider, Rene Celis-Cordova, Alexei Orlov, Tian Lu, Jason M. Kulick
  • Adiabatic Flip-Flop and Memory Cell Design
    Publication number: 20210327496
    Abstract: In a method computer storage element operation, first and second rising (or falling) clock edges are applied to first and second power inputs of the computer storage element having a transistor array between the first and second power inputs over time T1 whereupon a logic value applied to an input of the transistor array is stored therein. Thereafter, first and second falling (or rising) clock edges are applied to the first and second power inputs over time T2, whereupon part of an electrical charge or energy associated with the logic value stored in the transistor array is provided to circuitry that generates the first and/or second clock edge(s), wherein the value(s) of time T1 and/or time T2 is/are greater than a product of RC, where R is resistance associated with the computer storage element, and C is a load capacitance associated with the computer storage element.
    Type: Application
    Filed: February 19, 2021
    Publication date: October 21, 2021
    Inventors: Gregory Snider, Rene Celis-Cordova, Alexei Orlov, Tian Lu, Jason M. Kulick