Abstract: Test methods and structures are provided for electrically monitoring the image size tolerance (.DELTA.W) during a critical photolithographic step in the processing of a semiconductor wafer. The test structure includes two symmetrical resistor bridges combined into a single structure exhibiting a specific topology and having specific nominal parameters of length and width. The structure further includes contact regions and contact voltages are respectively measured across the first and second bridges. The size tolerance is determined from the voltages. Therefore, the factor .DELTA.W is directly determined by means of simple electrical measurements and, therefore, a data base is immediately provided with respect to the wafer in which the structure exists. Also, this invention relates to a method for monitoring the electrical tolerance (.DELTA.A) where images are superimposed, which uses the preceding calculation.