Abstract: A reset system for a digital electronic clock of the multistage counter type. Means are provided for deriving from the mains alternating current timing pulses at a frequency substantially higher than 1 Hz and a frequency divider chain derives from these timing pulses, resetting pulses at a frequency higher than 1 Hz and stepping on pulses for the seconds counter at a frequency of 1 Hz. The timing pulses are converted into gating signals by capacitative keys and resettable monostable circuits. The resetting pulses are applied to the counters through AND-gates controlled by the resettable monostable circuits and through OR-gates, the latter receiving also the pulses for stepping on the counters.