Abstract: An integrated circuit in dynamic MOS logic is composed of combinatory and sequential logic elements. Each of the latter comprises a succession of an input gate, an intermediate gate and an output gate which are activated to conduct by a corresponding phase of the first one and subsequent phases of a clock pulse cycle. The combinatory logic elements are all composed of gates of a single type, while the input signals are applied via the sequential logic elements and the output signals are output again via the latter elements. Thus, in the combinatory network only a sole type of interference is still relevant.

Abstract: A semiconductor device having an integrated circuit of which a region of one conductivity type is charged by supplying charge carriers from a zone of the opposite conductivity type to an inversion layer formed in the said region below a field electrode at which a voltage is set up. When the voltage is switched off, a part of the charge carriers recombine in the said region. According to the invention, the charge carriers are supplied from a supply conductor and an electronic switch is present between said conductor and the inversion layer, which switch prevents the flow back of charge carriers to the supply conductor when the inversion layer disappears.