Patents by Inventor Rene Marchand
Rene Marchand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9479001Abstract: A regulator draws power from a battery or power delivery system and supplies regulated power to a load according to alternating modes of operation. In a voltage control mode, the regulator supplies power with a nominal voltage level and a fluctuating current level that is allowed to float according to the current demands of the load. When the load demands an amount of current that could potentially cause damage, the regulator transitions to a current control mode. In the current control mode, the regulator supplies power with a fluctuating voltage level and a maximum current level. The regulator transitions between voltage control mode and current control mode in order to supply a maximum power level to the load without exceeding the maximum current level. The regulator is also configured to limit the power drawn from the battery by decreasing the maximum output current, potentially avoiding voltage droop.Type: GrantFiled: August 27, 2013Date of Patent: October 25, 2016Assignee: NVIDIA CORPORATIONInventors: Rene Marchand, Thomas Dean Skelton, Matthew Longnecker, Brian Smith
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Publication number: 20150061633Abstract: A regulator draws power from a battery or power delivery system and supplies regulated power to a load according to alternating modes of operation. In a voltage control mode, the regulator supplies power with a nominal voltage level and a fluctuating current level that is allowed to float according to the current demands of the load. When the load demands an amount of current that could potentially cause damage, the regulator transitions to a current control mode. In the current control mode, the regulator supplies power with a fluctuating voltage level and a maximum current level. The regulator transitions between voltage control mode and current control mode in order to supply a maximum power level to the load without exceeding the maximum current level. The regulator is also configured to limit the power drawn from the battery by decreasing the maximum output current, potentially avoiding voltage droop.Type: ApplicationFiled: August 27, 2013Publication date: March 5, 2015Applicant: NVIDIA CORPORATIONInventors: Rene MARCHAND, Thomas Dean SKELTON, Matthew LONGNECKER, Brian SMITH
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Patent number: 7024540Abstract: Port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF). With a manifold array (ManArray) reconfigurable register file, it is possible to have double-word 64-bit and single word 32-bit data-type instructions mixed with other double-word, single-word, half-word, or byte data-type instructions within the same very long instruction word (VLIW). By resolving a write priority conflict on the byte, half-word, or word that is in conflict during the VLIW execution, it is possible to have partial operations complete that provide a useful function. For example, a load half-word to the half-word H0 portion of a 32-bit register R0 can have priority to complete its operation while a 64-bit shift of the register pair R0 and R1 will complete its operation on the non-conflicting half-word portions of the 64-bit register R0 and R1.Type: GrantFiled: October 28, 2003Date of Patent: April 4, 2006Assignee: PTS CorporationInventors: Edwin Frank Barry, Edward A. Wolff, Patrick Rene Marchand, David Carl Strube
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Patent number: 6775766Abstract: A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages.Type: GrantFiled: February 28, 2001Date of Patent: August 10, 2004Assignee: PTS CorporationInventors: Juan Guillermo Revilla, Edwin F. Barry, Patrick Rene Marchand, Gerald G. Pechanek
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Publication number: 20040093484Abstract: Port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF). With a manifold array (ManArray) reconfigurable register file, it is possible to have double-word 64-bit and single word 32-bit data-type instructions mixed with other double-word, single-word, half-word, or byte data-type instructions within the same very long instruction word (VLIW). By resolving a write priority conflict on the byte, half-word, or word that is in conflict during the VLIW execution, it is possible to have partial operations complete that provide a useful function. For example, a load half-word to the half-word H0 portion of a 32-bit register R0 can have priority to complete its operation while a 64-bit shift of the register pair R0 and R1 will complete its operation on the non-conflicting half-word portions of the 64-bit register R0 and R1.Type: ApplicationFiled: October 28, 2003Publication date: May 13, 2004Applicant: PTS CorporationInventors: Edwin Frank Barry, Edward A. Wolff, Patrick Rene Marchand, David Carl Strube
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Patent number: 6654870Abstract: Port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF). With a manifold array (ManArray) reconfigurable register file, it is possible to have double-word 64-bit and single word 32-bit data-type instructions mixed with other double-word, single-word, half-word, or byte data-type instructions within the same very long instruction word (VLIW). By resolving a write priority conflict on the byte, half-word, or word that is in conflict during the VLIW execution, it is possible to have partial operations complete that provide a useful function. For. example, a load half-word to the half-word H0 portion of a 32-bit register R0 can have priority to complete its operation while a 64-bit shift of the register pair R0 and R1 will complete its operation on the non-conflicting half-word portions of the 64-bit register R0 and R1.Type: GrantFiled: June 21, 2000Date of Patent: November 25, 2003Assignee: PTS CorporationInventors: Edwin Frank Barry, Edward A. Wolff, Patrick Rene Marchand, David Carl Strube
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Publication number: 20030061473Abstract: A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages.Type: ApplicationFiled: February 28, 2001Publication date: March 27, 2003Inventors: Juan Guillermo Revilla, Edwin F. Barry, Patrick Rene Marchand, Gerald G. Pechanek
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Patent number: 6216223Abstract: A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages.Type: GrantFiled: January 12, 1999Date of Patent: April 10, 2001Assignee: Billions of Operations Per Second, Inc.Inventors: Juan Guillermo Revilla, Edwin F. Barry, Patrick Rene Marchand, Gerald G. Pechanek
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Patent number: 5945358Abstract: A papermaker's fabric is provided having a spun bonded reinforcement. A layer of spun bonded material may be placed in any one of a number of possible locations in the fabric, depending upon the felt stratification desired. For example, it may be attached to the upper surface (or paper contacting side) of the base fabric layer; to the lower surface (or machine contacting side) of the base fabric layer; between two base fabric layers, in the case of a laminated felt; between layers of fibers; or in any other desired location. The spun bonded material may be attached through the use of needling or by use of adhesives, low melts, or ultrasonic methods.Type: GrantFiled: January 31, 1996Date of Patent: August 31, 1999Assignee: Weavexx CorporationInventor: Rene Marchand
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Patent number: 5651394Abstract: A papermaker's fabric for use in the press section of a papermaking machine having a base fabric layer woven from either oval shaped monofilament yarns or "cabled monofilament oval yarns", which are cabled yarns comprised of two or more oval shaped monofilament yarns.Type: GrantFiled: February 2, 1996Date of Patent: July 29, 1997Assignee: Huyck Licensco, Inc.Inventor: Rene Marchand
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Patent number: 4989647Abstract: A papermakers' fabric, especially a forming fabric, for use on papermaking, cellulosic and similar machine, providing rigidity and wear resistance as well as an effective papermaking surface. The fabric has a papermaking surface in which single machine direction knuckles appear in a repeating diagonal pattern across the surface. An additional machine direction yarn passes between the single knuckles, over the two cross machine direction yarns and an additional cross machine direction yarn, on the papermaking surface thereby creating a machine direction knuckle between two single machine direction knuckles. An additional cross machine direction yarn is laced under the machine direction yarn knuckle on that surface.Type: GrantFiled: March 20, 1989Date of Patent: February 5, 1991Assignee: Huyck CorporaitonInventor: Rene Marchand