Abstract: Method and apparatus for reducing the time required to test an integrated circuit (10) using slew rate control. Using a very slow slew rate during normal operation may reduce electromagnetic interference, while using a faster slew rate during testing may reduce the test costs. In one embodiment, terminal control circuitry (40) includes a fast test control bit (50) to select a slow slew rate during normal operation, to select a faster slew rate during functional testing, and to optionally select a variety of slew rates during a special test to more fully characterize the behavior of integrated circuit (10). In one embodiment, each pre-driver circuit (80, 81) includes a low resistance device (61, 63) which may be selectively enabled or disabled to join with capacitors (66, 67) in output driver (82) to affect the slew rate of the signal driven as an output by integrated circuit terminal (83).