Abstract: An SMBus message handler, an integrated circuit and a method for controlling an SMBus are disclosed which identifies starting address of a program being stored in a memory. Instructions of the program are fetched one after another into a finite-state machine which controls the data transfer between an SMBus interface and a register set in compliance with the instruction present in the finite-state machine. Further, an SMBus test device and a method for controlling a testing system are described which check as to whether a key is input from a second interface. Upon inputting of a key it is mapped to a sequence of instructions for controlling devices connected to the SMBus or transferring data or receiving data from the devices connected to the SMBus.

Abstract: An SMBus message handler, an integrated circuit and a method for controlling an SMBus are disclosed which identifies starting address of a program being stored in a memory. Instructions of the program are fetched one after another into a finite-state machine which controls the data transfer between an SMBus interface and a register set in compliance with the instruction present in the finite-state machine. Further, an SMBus test device and a method for controlling a testing system are described which check as to whether a key is input from a second interface. Upon inputting of a key it is mapped to a sequence of instructions for controlling devices connected to the SMBus or transferring data or receiving data from the devices connected to the SMBus.

Abstract: An on-chip event timer apparatus including a hardware timer and a debug interface. The hardware timer includes at least an up-counter for counting clocks of a clock signal, a match register for storing a programmable count value, and a comparator for monitoring whether the up-counter's count value matches the count value of the match register. The debug interface includes enable control unit for enabling the up-counter's operation based on a pre-defined relationship between a state of an enabled signal supplied to said up-counter and an internal state of the hardware timer. Additionally, the debug interface may comprise a clock divider connected to the enable control unit to reduce the clock's frequency in accordance with a pre-programmed divider value. Based on the received clock with the reduced clock frequency, the enable control unit adapts the up-counter's processing speed to the reduced clock frequency.

Abstract: An on-chip event timer apparatus including a hardware timer and a debug interface. The hardware timer includes at least an up-counter for counting clocks of a clock signal, a match register for storing a programmable count value, and a comparator for monitoring whether the up-counter's count value matches the count value of the match register. The debug interface includes enable control unit for enabling the up-counter's operation based on a pre-defined relationship between a state of an enabled signal supplied to said up-counter and an internal state of the hardware timer. Additionally, the debug interface may comprise a clock divider connected to the enable control unit to reduce the clock's frequency in accordance with a pre-programmed divider value. Based on the received clock with the reduced clock frequency, the enable control unit adapts the up-counter's processing speed to the reduced clock frequency.