Patents by Inventor Renee T. Mo
Renee T. Mo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11018225Abstract: A method for forming an overlap transistor includes forming a gate structure over a III-V material, wet cleaning the III-V material on side regions adjacent to the gate structure and plasma cleaning the III-V material on the side regions adjacent to the gate structure. The III-V material is plasma doped on the side regions adjacent to the gate structure to form plasma doped extension regions that partially extend below the gate structure.Type: GrantFiled: June 28, 2016Date of Patent: May 25, 2021Assignee: International Business Machines CorporationInventors: Robert L. Bruce, Kevin K. Chan, Sebastian U. Engelmann, Renee T. Mo, Christopher Scerbo, Hongwen Yan, Jeng-Bang Yau
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Patent number: 10930565Abstract: A method of fabricating an n-type field effect transistor device (nFET) in a region of a wafer element is provided. The method includes forming a mandrel in the region and growing III-V semiconductor materials on the mandrel. The method also includes pulling the mandrel from a gate space in which a capped gate structure is formable and from source and drain (S/D) contact spaces and growing III-V semiconductor materials in the S/D contact spaces.Type: GrantFiled: November 1, 2018Date of Patent: February 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: HsinYu Tsai, Renee T. Mo, Cheng-Wei Cheng, Ko-Tao Lee
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Patent number: 10672671Abstract: Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.Type: GrantFiled: July 13, 2017Date of Patent: June 2, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan
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Publication number: 20200144123Abstract: A method of fabricating an n-type field effect transistor device (nFET) in a region of a wafer element is provided. The method includes forming a mandrel in the region and growing III-V semiconductor materials on the mandrel. The method also includes pulling the mandrel from a gate space in which a capped gate structure is formable and from source and drain (S/D) contact spaces and growing III-V semiconductor materials in the S/D contact spaces.Type: ApplicationFiled: November 1, 2018Publication date: May 7, 2020Inventors: HsinYu Tsai, Renee T. Mo, Cheng-Wei Cheng, Ko-Tao Lee
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Patent number: 10593600Abstract: Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.Type: GrantFiled: February 24, 2016Date of Patent: March 17, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan
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Patent number: 10580686Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.Type: GrantFiled: May 25, 2018Date of Patent: March 3, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony I. Chou, Arvind Kumar, Renee T. Mo, Shreesh Narasimha
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Publication number: 20200066724Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.Type: ApplicationFiled: November 1, 2019Publication date: February 27, 2020Inventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan, John Rozen
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Patent number: 10553584Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.Type: GrantFiled: June 19, 2018Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan, John Rozen
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Publication number: 20200027779Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.Type: ApplicationFiled: September 27, 2019Publication date: January 23, 2020Inventors: Anthony I. Chou, Arvind Kumar, Renee T. Mo, Shreesh Narasimha
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Patent number: 10504799Abstract: Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.Type: GrantFiled: July 13, 2017Date of Patent: December 10, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan
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Patent number: 10396077Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.Type: GrantFiled: June 19, 2018Date of Patent: August 27, 2019Assignee: International Business Machines CorporationInventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan, John Rozen
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Patent number: 10361304Abstract: A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.Type: GrantFiled: June 18, 2018Date of Patent: July 23, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Isaac Lauer, Jiaxing Liu, Renee T. Mo
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Publication number: 20190181037Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.Type: ApplicationFiled: February 13, 2019Publication date: June 13, 2019Inventors: Anthony I. Chou, Arvind Kumar, Renee T. Mo, Shreesh Narasimha
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Patent number: 10246745Abstract: A semiconductor structure is provided that can be used for DNA sequencing detection. The semiconductor structure includes a doped epitaxial source semiconductor material structure located on a first portion of a semiconductor substrate and a doped epitaxial drain semiconductor material structure located on a second portion of the semiconductor substrate. A gate dielectric portion is located on a third portion of the semiconductor substrate and positioned between the doped epitaxial source semiconductor material structure and the doped epitaxial drain semiconductor material structure. A non-stick nucleotide, DNA and DNA polymerase material structure is located atop the doped epitaxial source semiconductor material structure and atop the doped epitaxial drain semiconductor material structure, wherein a cavity is present in the non-stick nucleotide, DNA and DNA polymerase material structure that exposes a topmost surface of the gate dielectric portion.Type: GrantFiled: April 20, 2018Date of Patent: April 2, 2019Assignee: International Business Machines CorporationInventors: Sanghoon Lee, Effendi Leobandung, Renee T. Mo
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Patent number: 10242906Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.Type: GrantFiled: August 4, 2017Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Arvind Kumar, Renee T. Mo, Shreesh Narasimha
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Patent number: 10205003Abstract: A method for use in forming a fin of a field-effect transistor includes: patterning a mandrel into a substrate at least by recessing portions of the substrate; forming dielectric material at least on the recessed portions of the substrate, wherein the dielectric material partially covers exterior sidewalls of the mandrel; forming a first buffer at least on a portion of the exterior sidewalls of the mandrel not covered by the dielectric material; forming a second buffer at least on exterior sidewalls of the first buffer; forming a semiconductor channel at least on the dielectric material, wherein at least the second buffer is between the channel and the mandrel; exposing interior sidewalls of at least the first buffer at least by removing the mandrel; and removing the first buffer and the second buffer without removing the channel.Type: GrantFiled: January 15, 2018Date of Patent: February 12, 2019Assignee: International Business Machines CorporationInventors: Cheng-Wei Cheng, Sanghoon Lee, Effendi Leobandung, Renee T. Mo
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Publication number: 20180308976Abstract: A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.Type: ApplicationFiled: June 18, 2018Publication date: October 25, 2018Inventors: Isaac Lauer, Jiaxing Liu, Renee T. Mo
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Publication number: 20180308845Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.Type: ApplicationFiled: June 19, 2018Publication date: October 25, 2018Inventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan, John Rozen
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Publication number: 20180308844Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.Type: ApplicationFiled: June 19, 2018Publication date: October 25, 2018Inventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan, John Rozen
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Patent number: 10109737Abstract: A method of forming high germanium content silicon germanium alloy fins with controlled insulator layer recessing is provided. A silicon germanium alloy (SiGe) layer having a first germanium content is provided on a surface of an insulator layer using a first condensation process. Following the formation of a hard mask layer portion on the SiGe layer, a second condensation process is performed to convert a portion of the SiGe layer into a SiGe fin of a second germanium content that is greater than the first germanium content and other portions of the SiGe layer into a shell oxide structure located on sidewalls of the SiGe fin. After forming a fin placeholder material, a portion of each shell oxide structure is removed, while maintaining a lower portion of each shell oxide structure at the footprint of the SiGe fin.Type: GrantFiled: June 5, 2017Date of Patent: October 23, 2018Assignee: International Business Machines CorporationInventors: Pouya Hashemi, Renee T. Mo, John A. Ott, Alexander Reznicek