Abstract: A data storage method, apparatus, and device, and a readable storage medium. The method includes: after a random access memory is powered on, obtaining target data to be stored in a fixed storage address of the random access memory; determining a target transmission mode from a bit value change transmission mode and a bit value fixed transmission mode, wherein the target transmission mode is different from a historical transmission mode determined after the random access memory is powered on last time; and transmitting the target data from and to the random access memory according to the target transmission mode. The method can prevent data from being stolen after power-down of the target data, and guarantees the data security.

Abstract: A quantum data erasure method, system and device, and a readable storage medium. The method includes: acquiring an equal-probability quantum state system; measuring the equal-probability quantum state system to collapse the equal-probability quantum state system into a binary random number sequence; generating a corresponding random angle value according to the binary random number sequence; and performing a bitwise rotation operation on quantum data in a quantum device according to the random angle value to complete this quantum data erasure. In the present application, the introduction of a quantum true random number can ensure that erased data will not be recovered and reversely cracked, and is of great value in protecting data assets; moreover, randomly processed data still has the characteristics such as quantum coherence and quantum entanglement, and can be used in subsequent operations, whereby a time-consuming labor-intensive process of preparing a quantum system is not required every time.

Abstract: Provided are an image data storage method, an image data processing method and system, and a related apparatus. The image data processing method includes the following steps: sequentially storing image data in a dynamic random memory according to a preset storage format, so that adjacent pieces of image data in the dynamic random memory have continuous storage addresses; reading a preset number of pieces of multi-channel parallel image data from the dynamic random memory, and storing the multi-channel parallel image data in a first-in first-out memory of an FPGA; and executing a convolution operation on target image data in the first-in first-out memory to obtain image feature data. By means of the method, the image data processing rate can be increased.

Abstract: A system for accelerating an RNN network including: a first cache, which is used for outputting Wx1 to WxN or Wh1 to WhN in parallel in N paths in a cyclic switching manner, and the degree of parallelism is k; a second cache, which is used for outputting xt or ht-1 in the cyclic switching manner; a vector multiplication circuit, which is used for, by using N groups of multiplication arrays, respectively calculating Wx1xt to WxNxt, or respectively calculating Wh1ht-1 to WhNht-1; an addition circuit, which is used for calculating Wx1xt+Wh1ht-1+b1 to WxNxt+WhNht-1+bN; an activation circuit, which is used for performing an activation operation according to an output of the addition circuit; a state updating circuit, which is used for acquiring ct-1, calculating ct and ht, updating ct-1, and sending ht to the second cache; a bias data cache; a vector cache; and a cell state cache.

Abstract: A data storage method, apparatus, and device, and a readable storage medium. The method includes: after a random access memory is powered on, obtaining target data to be stored in a fixed storage address of the random access memory; determining a target transmission mode from a bit value change transmission mode and a bit value fixed transmission mode, wherein the target transmission mode is different from a historical transmission mode determined after the random access memory is powered on last time; and transmitting the target data from and to the random access memory according to the target transmission mode. The method can prevent data from being stolen after power-down of the target data, and guarantees the data security.

Abstract: Provided are a turbulence field update method, apparatus, and device, and a computer-readable storage medium. The method includes: obtaining sample turbulence data; performing model training by use of the sample turbulence data to obtain a reinforcement learning turbulence model; calculating initial turbulence data of a turbulence field by use of a Reynolds Averaged Navior-Stokes (RANS) equation; processing the initial turbulence data by use of the reinforcement learning turbulence model to obtain a predicted Reynolds stress; and performing calculation on the predicted Reynolds stress by use of the RANS equation to obtain updated turbulence data.

Abstract: A data processing method, a data processing apparatus, a distributed data flow programming framework, an electronic device, and a storage medium. The data processing method includes: dividing a data processing task into a plurality of data processing subtasks (S101); determining, in a Field Programmable Gate Array (FPGA) accelerator side, a target FPGA acceleration board corresponding to each of the data processing subtasks (S102); and sending data to be computed to the target FPGA acceleration board, and executing the corresponding data processing subtask by use of each of the target FPGA acceleration boards to obtain a data processing result (S103). According to the method, a physical limitation of host interfaces on the number of FPGA acceleration boards in an FPGA accelerator side may be avoided, thereby improving the data processing efficiency.

Abstract: The present invention provides a method and apparatus for data caching. The method comprises: output matrixes are acquired one by one, a plurality of acquired output matrixes are written alternately into two queue sets of a first cache unit according to a sequence in which the output matrixes are acquired, and the output matrixes stored line by line in a first cache unit are written into a second cache unit one by one, according to the sequence in which the output matrixes are written into the second cache unit, valid data of each output matrix of the second cache unit is determined one by one according to preset parameters, and the valid data of each output matrix is written into a third cache unit, and the valid data of the output matrixes stored in the third cache unit are configured to be sequentially written into a memory according to a sequence in which the valid data are written into the third cache unit.

Abstract: A RISC-V branch prediction method and device, an electronic device and a computer readable storage medium are provided. On the basis of the prior art, the remaining jump times of the jump instruction are additionally acquired, and the single jump step length (the single jump step length is not fixed to be 1) is calculated according to the difference of remaining jump times during two consecutive jumps, whether the target jump instruction has executed the last jump can be judged according to the single jump step length of a jump instruction and in combination with the real-time remaining jump times, so as to determine the jump times that need to be executed subsequently according to the judgment result.

Abstract: A high-resolution image matching method and system are provided. The method includes performing regional fidelity down-sampling on an initial high-resolution image to obtain a multi-level low-resolution image, performing local matching on the obtained multi-level low-resolution images using a method with global probes to obtain a matching result of the low-resolution images, and performing reverse refinement on the obtained matching result of the low-resolution image using overall consistency of the image matching, to obtain the matching results of the high-resolution images at all levels until the matching results of the initial resolution images are obtained, so as to reduce the computational complexity of the image matching process and improve the accuracy of the matching result, and then the matching result of the high-resolution image is obtained through reverse refinement based on the overall consistency.

Abstract: A hybrid heterogeneous host system, a resource configuration method and a task scheduling method are disclosed. The system includes: a basic unit, including: computing resource nodes, storage resource nodes and input/output I/O resource nodes; wherein multiple basic units are connected via a high-speed internetwork; and a software definition unit, configured to: when system resources are increased or reduced, extend the address space of an increased hardware resource to a current address space, or delete an address space of a reduced hardware resource from the current address space, and update a system resource view. Through the embodiments of the present invention, the extendibility of a tightly coupled shared memory system can be guaranteed, and the design complexity and cost of the multiway system also can be greatly reduced, which improves the flexibility and reusability of the system.

Abstract: A method and system for implementing a directory structure of a host system are disclosed. The method includes: multiple basic computing units interconnecting via a high speed internetwork to construct a system computing unit set; wherein each basic computing unit comprises a protocol processing chip and a system resource management firmware; and dividing a part implementing a logic function in the protocol processing chip into a static part and a dynamic part in advance, wherein the dynamic part can be reconstructed; constructing a system cache directory storage architecture through the dynamic part; and the system resource management firmware managing system resources by means of configuration.

Abstract: A method and system for implementing a directory structure of a host system are disclosed. The method includes: multiple basic computing units interconnecting via a high speed internetwork to construct a system computing unit set; wherein each basic computing unit comprises a protocol processing chip and a system resource management firmware; and dividing a part implementing a logic function in the protocol processing chip into a static part and a dynamic part in advance, wherein the dynamic part can be reconstructed; constructing a system cache directory storage architecture through the dynamic part; and the system resource management firmware managing system resources by means of configuration.

Abstract: A differential signal reversion and correction circuit and a method thereof are provided. The structures of the circuit include: a data frame sending module, when the link conditions are detected, the data frame sending module generates specific logic sequence and finishes the sending by a input/output port, such that a receiving side receives, processes and analyzes the sequence, and determination of link transmission conditions are achieved; a comparator of the receiving side, which receives sequence data, performs corresponding comparing, checking and feedback controlling, thereby achieving link detection and differential correction purpose; a reversion control signal generating module, which receives a comparison result of the comparator, generates corresponding control signal, and controls the link whether to perform reversion operation.

Abstract: A hybrid heterogeneous host system, a resource configuration method and a task scheduling method are disclosed. The system includes: a basic unit, including: computing resource nodes, storage resource nodes and input/output I/O resource nodes; wherein multiple basic units are connected via a high-speed internetwork; and a software definition unit, configured to: when system resources are increased or reduced, extend the address space of an increased hardware resource to a current address space, or delete an address space of a reduced hardware resource from the current address space, and update a system resource view. Through the embodiments of the present invention, the extendibility of a tightly coupled shared memory system can be guaranteed, and the design complexity and cost of the multiway system also can be greatly reduced, which improves the flexibility and reusability of the system.

Abstract: A design method of a repeater chip is provided, the repeater chip designed by using the method can implement interconnection among nodes, and implement packet sequence receiving, classifying, storing, forwarding, sorting, and transmitting functions of the repeater chip, thereby implementing effective extension of a high-speed transmission link among the nodes, so as to reduce hardware design difficulties and design risks. The structure of the repeater chip is formed by: an interface detecting unit, a sequence storing unit, a sequence forwarding unit, a sequence determining unit, and a sequence sorting unit.

Abstract: A differential signal reversion and correction circuit and a method thereof are provided. The structures of the circuit include: a data frame sending module, when the link conditions are detected, the data frame sending module generates specific logic sequence and finishes the sending by a input/output port, such that a receiving side receives, processes and analyzes the sequence, and determination of link transmission conditions are achieved; a comparator of the receiving side, which receives sequence data, performs corresponding comparing, checking and feedback controlling, thereby achieving link detection and differential correction purpose; a reversion control signal generating module, which receives a comparison result of the comparator, generates corresponding control signal, and controls the link whether to perform reversion operation.

Abstract: A method of implementing packet search by double sliding windows is provided. The method adopts a three-level barrel shift register to store input packet data, and a position of a sliding window 1 is determined at 32 positions by primary testing of a link, so as to ensure that the packet data is located at the center of the sliding window 1, thereby ensuring that the position of the sliding window 1 meets a transmission characteristic of a specific link to the maximum extent. After the position of the sliding window 1 is determined, 32-bit packet data can be effectively searched in the sliding window 1 by dynamically adjusting a sliding window 2, and 32-bit transmission offset is allowed for the packet data. The method of implementing packet search by double sliding windows meets a transmission characteristic of a specific link to the maximum extent.

Abstract: A design method of a repeater chip is provided, the repeater chip designed by using the method can implement interconnection among nodes, and implement packet sequence receiving, classifying, storing, forwarding, sorting, and transmitting functions of the repeater chip, thereby implementing effective extension of a high-speed transmission link among the nodes, so as to reduce hardware design difficulties and design risks. The structure of the repeater chip is formed by: an interface detecting unit, a sequence storing unit, a sequence forwarding unit, a sequence determining unit, and a sequence sorting unit.

Abstract: A prototype verification system and method are provided for a high-end fault-tolerant computer. The system includes multiple single junction prototype verification systems and an interconnection router chipset. The single junction prototype verification systems are interconnected through the interconnection router chipset. Each single junction prototype verification system includes a computer board which is a four-path tightly-coupled computer board, and a chip verification board including two junction controller chipsets. Each junction controller chipset includes two field-programmable gate array (FGPA) chips which bear a logic of one junction controller together, and an interconnection board including two FGPA chips. Each FPGA chip provides a high speed interconnection port used to achieve protocol interconnection between two paths of the computer board and one of the junction controller chipsets.