Patents by Inventor Rengarajan S. Krishnan

Rengarajan S. Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Match mismatch emulation scheme for an addressed location in a CAM
    Patent number: 7471536
    Abstract: A novel match/mismatch emulation scheme for an addressed location in a CAM system that includes a plurality of CAM blocks. The plurality of CAM blocks are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group of CAM cells to an addressed search circuit. During debug mode, where the individual array cells do not participate in search, all the cells in the debug column behave the same way to emulate a match/mismatch on all words. The circuit provides a control input to include address evaluation of a debug cell in a row. The circuit also provides simultaneous switching noise analysis on an evaluating row. The resulting CAM cell provides a circuit to test individual rows for defects and noise analysis.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: December 30, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Rengarajan S Krishnan, Rashmi Sachan, Bryan D Sheffield, Nisha Padattil Kuliyampattil
  • NOVEL MATCH MISMATCH EMULATION SCHEME FOR AN ADDRESSED LOCATION IN A CAM
    Publication number: 20080137388
    Abstract: A novel match/mismatch emulation scheme for an addressed location in a CAM system that includes a plurality of CAM blocks. The plurality of CAM blocks are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group of CAM cells to an addressed search circuit. During debug mode, where the individual array cells do not participate in search, all the cells in the debug column behave the same way to emulate a match/mismatch on all words. The circuit provides a control input to include address evaluation of a debug cell in a row. The circuit also provides simultaneous switching noise analysis on an evaluating row. The resulting CAM cell provides a circuit to test individual rows for defects and noise analysis.
    Type: Application
    Filed: December 8, 2006
    Publication date: June 12, 2008
    Inventors: Rengarajan S. Krishnan, Rashmi Sachan, Bryan D. Sheffield, Nisha Padattil Kuliyampattil
  • Memory based phase locked loop
    Patent number: 6625765
    Abstract: A circuit comprising a phase detector/correction circuit, at least one column of memory cells, a control circuit and a sense amplifier. The control circuit may be configured to read a sequence from the memory cells in a predetermined order and present a first output signal. The sense amplifier may be configured to present a periodic signal in response to the first output signal.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: September 23, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventor: Rengarajan S. Krishnan