Patents by Inventor Rengarajan SHANMUGAM

Rengarajan SHANMUGAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240006258
    Abstract: Substrates with nitrided glass cores, and methods of forming the same, are described herein. In one example, a substrate includes one or more glass layers and a plurality of dielectric layers. At least one of the glass layers includes nitrogen. Further, at least one of the dielectric layers is above the one or more glass layers and at least one of the dielectric layers is below the one or more glass layers.
    Type: Application
    Filed: July 2, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Suddhasattwa Nad, Darko Grujicic, Rengarajan Shanmugam
  • Publication number: 20230420358
    Abstract: Disclosed herein are silver-coated conductive structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a first material layer on a top surface and on side surfaces of the conductive line, the first material layer including silver, and a second material layer on the first material layer, the second material layer including silicon or aluminum, and one or more of nitrogen and oxygen.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 28, 2023
    Applicant: Intel Corporation
    Inventors: Cemil S. Geyik, Kristof Kuwawi Darmawikarta, Zhiguo Qian, Kemal Aygun, Jung Kyu Han, Srinivas V. Pietambaram, Rengarajan Shanmugam, Robert L. Sankman
  • Patent number: 11728265
    Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: August 15, 2023
    Assignee: Intel Corporation
    Inventors: Brandon C. Marin, Frank Truong, Shivasubramanian Balasubramanian, Dilan Seneviratne, Yonggang Li, Sameer Paital, Darko Grujicic, Rengarajan Shanmugam, Melissa Wette, Srinivas Pietambaram
  • Publication number: 20230107096
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to glass layers within a package that include one or more high aspect ratio TGV that are filled with conductive material. The TGV extends from a first side of the glass layer to a second side of the glass layer opposite the first side and are filled with conductive material to provide a high-quality electrical connection between the first side of the glass layer and the second side of the glass layer, where a portion of the wall of the TGV includes titanium. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 21, 2021
    Publication date: April 6, 2023
    Inventors: Darko GRUJICIC, Sashi S. KANDANUR, Helme A. CASTRO DE LA TORRE, Srinivas V. PIETAMBARAM, Marcel WALL, Suddhasattwa NAD, Rengarajan SHANMUGAM, Benjamin DUONG
  • Publication number: 20230095846
    Abstract: Glass substrates having transverse capacitors for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a glass substrate having a through glass via between a first surface and a second surface opposite the first surface. A transverse capacitor is located in the through glass via. The transverse capacitor includes a dielectric material positioned in a first portion of the through glass via, a first barrier/seed layer positioned in a second portion of the through glass via, and a first conductive material positioned in a third portion of the through glass via.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Benjamin T. Duong, Srinivas V. Pietambaram, Aleksandar Aleksov, Helme Castro De La Torre, Kristof Darmawikarta, Darko Grujicic, Sashi S. Kandanur, Suddhasattwa Nad, Rengarajan Shanmugam, Thomas I. Sounart, Marcel A. Wall
  • Publication number: 20230091666
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: Benjamin DUONG, Aleksandar ALEKSOV, Helme A. CASTRO DE LA TORRE, Kristof DARMAWIKARTA, Darko GRUJICIC, Sashi S. KANDANUR, Suddhasattwa NAD, Srinivas V. PIETAMBARAM, Rengarajan SHANMUGAM, Thomas L. SOUNART, Marcel WALL
  • Publication number: 20230082385
    Abstract: An electronic device comprises an electronic package with a glass core. The glass core includes a first surface and a second surface opposite the first surface, at least one through-glass via (TGV) extending through the glass core from the first surface to the second surface, and including an electrically conductive material, and wherein the at least one TGV includes a first portion having a first width and a second portion having a second width different from the first width.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 16, 2023
    Inventors: Jeremy D. Ecton, Kristof Darmawikarta, Sashi S. Kandanur, Srinivas Venkata Ramanuja Pietambaram, Darko Grujicic, Marcel Arlan Wall, Suddhasattwa Nad, Benjamin Duong, Rengarajan Shanmugam, Bai Nie, Helme Castro De La Torre
  • Patent number: 11574993
    Abstract: Embodiments disclosed herein include electronic packages with embedded magnetic materials and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment a plurality of passive components is located in a first dielectric layer of the plurality of dielectric layers. In an embodiment, first passive components of the plurality of passive components each comprise a first magnetic material, and second passive components of the plurality of passive components each comprise a second magnetic material. In an embodiment, a composition of the first magnetic material is different than a composition of the second magnetic material.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: February 7, 2023
    Assignee: Intel Corporation
    Inventors: Rengarajan Shanmugam, Suddhasattwa Nad, Darko Grujicic, Srinivas Pietambaram
  • Patent number: 11291122
    Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Darko Grujicic, Rengarajan Shanmugam, Sandeep Gaan, Adrian Bayraktaroglu, Roy Dittler, Ke Liu, Suddhasattwa Nad, Marcel A. Wall, Rahul N. Manepalli, Ravindra V. Tanikella
  • Publication number: 20220093535
    Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Benjamin Duong, Roy Dittler, Darko Grujicic, Chandrasekharan Nair, Rengarajan Shanmugam
  • Publication number: 20220010452
    Abstract: The present disclosure is directed to an electroless plating process using a panel basket for holding semiconductor panels comprising a plurality of metal pads and shielding the metal pads from contaminants and over-etching and under-etching caused by the contaminants.
    Type: Application
    Filed: September 23, 2021
    Publication date: January 13, 2022
    Inventors: Chandrasekharan NAIR, Darko GRUJICIC, Rengarajan SHANMUGAM, Srinivasan RAMAN, Roy DITTLER, Daniel SOWA, Robert BARESEL, II, Marcel WALL, Rahul MANEPALLI
  • Publication number: 20210090946
    Abstract: Embodiments herein relate to systems, apparatuses, and/or processes directed to a package or a manufacturing process flow for creating a package that uses multiple seeding techniques to fill vias in the package. Embodiments include a first layer of copper seeding coupled with a portion of the boundary surface and a second layer of copper seeding coupled with the boundary surface or the first layer of copper seeding, where the first layer of copper seeding and the second layer of copper seeding have a combined thickness along the boundary surface that is greater than a threshold value.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Darko GRUJICIC, Matthew ANDERSON, Adrian BAYRAKTAROGLU, Roy DITTLER, Benjamin DUONG, Tarek A. IBRAHIM, Rahul N. MANEPALLI, Suddhasattwa NAD, Rengarajan SHANMUGAM, Marcel WALL
  • Publication number: 20200258975
    Abstract: Embodiments disclosed herein include electronic packages with embedded magnetic materials and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment a plurality of passive components is located in a first dielectric layer of the plurality of dielectric layers. In an embodiment, first passive components of the plurality of passive components each comprise a first magnetic material, and second passive components of the plurality of passive components each comprise a second magnetic material. In an embodiment, a composition of the first magnetic material is different than a composition of the second magnetic material.
    Type: Application
    Filed: February 8, 2019
    Publication date: August 13, 2020
    Inventors: Rengarajan SHANMUGAM, Suddhasattwa NAD, Darko GRUJICIC, Srinivas PIETAMBARAM
  • Publication number: 20200245472
    Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 22, 2017
    Publication date: July 30, 2020
    Inventors: Darko GRUJICIC, Rengarajan SHANMUGAM, Sandeep GAAN, Adrian BAYRAKTAROGLU, Roy DITTLER, Ke LIU, Suddhasattwa NAD, Marcel A. WALL, Rahul N. MANEPALLI, Ravindra V. TANIKELLA
  • Publication number: 20200083164
    Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 12, 2020
    Inventors: Brandon C. MARIN, Frank TRUONG, Shivasubramanian BALASUBRAMANIAN, Dilan SENEVIRATNE, Yonggang LI, Sameer PAITAL, Darko GRUJICIC, Rengarajan SHANMUGAM, Melissa WETTE, Srinivas PIETAMBARAM