Patents by Inventor Renichi Yamada

Renichi Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11016138
    Abstract: A diagnostic system for a power conversion apparatus including a semiconductor device and performing a switching operation for carrying and interrupting a main current to a main current is disclosed. This system includes a trigger circuit that acquires reference time for the switching operation; and a delay time calculation circuit that acquires first time at which the main current takes a first main current set value and second time at which the main current takes a second main current set value, and that detects numerical data about a difference between the first time and the reference time and numerical data about a difference between the second time and the reference time.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: May 25, 2021
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinobu Kimura, Junichi Sakano, Kimihisa Furukawa, Takashi Ogawa, Renichi Yamada
  • Publication number: 20190146026
    Abstract: A diagnostic system for a power conversion apparatus including a semiconductor device and performing a switching operation for carrying and interrupting a main current to a main current is disclosed. This system includes a trigger circuit that acquires reference time for the switching operation; and a delay time calculation circuit that acquires first time at which the main current takes a first main current set value and second time at which the main current takes a second main current set value, and that detects numerical data about a difference between the first time and the reference time and numerical data about a difference between the second time and the reference time.
    Type: Application
    Filed: May 9, 2016
    Publication date: May 16, 2019
    Inventors: Yoshinobu KIMURA, Junichi SAKANO, Kimihisa FURUKAWA, Takashi OGAWA, Renichi YAMADA
  • Patent number: 9846133
    Abstract: Provided are an inspection device that detects with high precision and classifies surface unevenness, step batching, penetrating blade-shaped dislocations, penetrating spiral dislocations, basal plane dislocations, and stacking defects formed in an SiC substrate and an epitaxial layer; and a system. In the inspection device using charged particle beams, a device is used that has an electrode provided between a sample and an objective lens, the device applies a positive or negative voltage to the electrode and obtains images. A secondary electron emission rate is measured and energy EL and EH for the charged particles are found. A first image is obtained using the EH and positive potential conditions. A second image is obtained using the EL and negative potential conditions. A third image is obtained at the same position as the second image, and by using the EL and positive potential conditions.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: December 19, 2017
    Assignee: HITACHI, LTD.
    Inventors: Yoshinobu Kimura, Natsuki Tsuno, Hiroya Ohta, Renichi Yamada, Toshiyuki Ohno, Yuki Mori
  • Patent number: 9508611
    Abstract: In a semiconductor inspection method using a semiconductor inspection device, by selecting an incident energy and a negative potential and scanning an inspection surface of a wafer with primary electrons to detect secondary electrons, a first inspection image is acquired, and a macro defect, stacking faults, a basal plane dislocation and a threading dislocation contained in the first inspection image are discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance. Moreover, by selecting the incident energy and a positive potential and scanning the inspection surface of the wafer with primary electrons to detect the secondary electrons, a second inspection image is acquired, and a threading screw dislocation of a dot-shaped figure contained in the second inspection image is discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: November 29, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinobu Kimura, Natsuki Tsuno, Hiroya Ohta, Renichi Yamada, Hirotaka Hamamura, Toshiyuki Ohno, Hiroyuki Okino, Yuki Mori
  • Publication number: 20160190020
    Abstract: In a semiconductor inspection method using a semiconductor inspection device, by selecting an incident energy and a negative potential and scanning an inspection surface of a wafer with primary electrons to detect secondary electrons, a first inspection image is acquired, and a macro defect, stacking faults, a basal plane dislocation and a threading dislocation contained in the first inspection image are discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance. Moreover, by selecting the incident energy and a positive potential and scanning the inspection surface of the wafer with primary electrons to detect the secondary electrons, a second inspection image is acquired, and a threading screw dislocation of a dot-shaped figure contained in the second inspection image is discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance.
    Type: Application
    Filed: August 14, 2013
    Publication date: June 30, 2016
    Inventors: Yoshinobu KIMURA, Natsuki TSUNO, Hiroya OHTA, Renichi YAMADA, Hirotaka HAMAMURA, Toshiyuki OHNO, Hiroyuki OKINO, Yuki MORI
  • Publication number: 20150303030
    Abstract: Provided are an inspection device that detects with high precision and classifies surface unevenness, step batching, penetrating blade-shaped dislocations, penetrating spiral dislocations, basal plane dislocations, and stacking defects formed in an SiC substrate and an epitaxial layer; and a system. In the inspection device using charged particle beams, a device is used that has an electrode provided between a sample and an objective lens, said device being capable of applying a positive or negative voltage to the electrode and obtaining images. A secondary electron emission rate is measured and energy EL and EH for the charged particles are found. First, an image (first image) is obtained using the EH and positive potential conditions. Next, an image (second image) is obtained using the EL and negative potential conditions. Next, an image (third image) is obtained at the same position as the second image, and by using the EL and positive potential conditions.
    Type: Application
    Filed: November 19, 2012
    Publication date: October 22, 2015
    Inventors: Yoshinobu Kimura, Natsuki Tsuno, Hiroya Ohta, Renichi Yamada, Toshiyuki Ohno, Yuki Mori
  • Patent number: 7450458
    Abstract: The present invention enables screening of the so-called variable retention time (VRT) failure, namely a retention failure occurring in a DRAM due to fluctuation of a data retention time like a random telegraph noise. A pause/refresh test for checking a data retention function is repeated at all memory cells of a chip so that memory cells at which the retention failure due to random fluctuation of the data retention capability over time may occur is subjected to screening.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: November 11, 2008
    Assignees: Hitachi, Ltd., Elpida Memory, Inc.
    Inventors: Yuki Mori, Renichi Yamada, Shuichi Tsukada, Kiyonori Oyu
  • Patent number: 7247890
    Abstract: Disclosed is herein a semiconductor device having a DRAM with less scattering of threshold voltage of MISFET in a memory cell and having good charge retainability of a capacitor, and a manufacturing method of the semiconductor device. An anti-oxidation film is formed to the side wall of a gate electrode before light oxidation thereby suppressing the oxidation of the side wall for the gate electrode and decreasing scattering of the thickness of the film formed to the sidewall in an asymmetric diffusion region structure in which the impurity concentration of an n-type semiconductor region and a p-type semiconductor region on the side of the data line is made relatively higher than the impurity concentration in the n-type semiconductor region and p-type semiconductor region on the side of the capacitor, respectively.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: July 24, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Tomoko Sekiguchi, Shinichiro Kimura, Renichi Yamada, Kikuo Watanabe, Hiroshi Miki, Kenichi Takeda
  • Publication number: 20060203590
    Abstract: The present invention enables screening of the so-called variable retention time (VRT) failure, namely a retention failure occurring in a DRAM due to fluctuation of a data retention time like a random telegraph noise. A pause/refresh test for checking a data retention function is repeated at all memory cells of a chip so that memory cells at which the retention failure due to random fluctuation of the data retention capability over time may occur is subjected to screening.
    Type: Application
    Filed: January 30, 2006
    Publication date: September 14, 2006
    Inventors: Yuki Mori, Renichi Yamada, Shuichi Tsukada, Kiyonori Oyu
  • Publication number: 20050098813
    Abstract: Disclosed is herein a semiconductor device having a DRAM with less scattering of threshold voltage of MISFET in a memory cell and having good charge retainability of a capacitor, and a manufacturing method of the semiconductor device. An anti-oxidation film is formed to the side wall of a gate electrode before light oxidation thereby suppressing the oxidation of the side wall for the gate electrode and decreasing scattering of the thickness of the film formed to the sidewall in an asymmetric diffusion region structure in which the impurity concentration of an n-type semiconductor region and a p-type semiconductor region on the side of the data line is made relatively higher than the impurity concentration in the n-type semiconductor region and p-type semiconductor region on the side of the capacitor, respectively.
    Type: Application
    Filed: September 1, 2004
    Publication date: May 12, 2005
    Inventors: Tomoko Sekiguchi, Shinichiro Kimura, Renichi Yamada, Kikuo Watanabe, Hiroshi Miki, Kenichi Takeda