Abstract: A method and system provide for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages. The method comprising the following steps. Inspect semiconductor devices on the wafer visually to identify the location of visual defects on dies being manufactured on the wafer and to maintain a count of visual defects on the dies by location. Inspect the semiconductor dies on the wafer to determine the location and number defective dies on the wafer at each of the manufacturing stages. Calculate the defective die count for each stage for the wafer. Calculate the defective bad die count for each stage for the wafer. Determine the percentage of the defective bad die count divided by the defective die count. Plot the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages.

Abstract: A method for determining stress effects, or stress endurance of a film layer coated on a wafer during a scrubber clean process is disclosed. In the method, a wafer having a film layer coated on top is held in a stationary position while a high pressure water jet having a pressure larger than 60 kg/cm2 is scanned across a top surface of the film layer and through a center of the wafer. The total number of stress defects is then counted in the scanning path on top of the film layer as an indication of the stress endurance of the specific coating layer. The invention also discloses a method for scrubber cleaning a wafer surface which is coated with a film layer without causing stress defects in the film by rotating a silicon wafer, which has a film layer coated on top at a suitable rotational speed, and then scanning a water jet across a top surface of the film layer without passing through a center of the wafer. The water pressure utilized for the water jet may be suitably between 50 kg/cm2 and 75 kg/cm2.

Abstract: A method for determining a cause for defect formation in an insulating material layer deposited on an electrically conductive layer on a wafer surface is disclosed. In the method, on top of a semi-conducting wafer which has a first insulating material layer deposited, a second insulating material layer is deposited to replace an electrically conductive layer. A third insulating material layer is then deposited on top of the second insulating layer and a water jet which has a high pressure is scanned across a top surface of the third insulating layer with the wafer held in a stationary position. Surface defects are then counted in the predetermined path on the top surface of the third insulating layer for determining the cause for defect formation. When no defects are found, the formation is attributed to electrostatic discharges occurring in the metal conductive layer.

Abstract: A method and system provide for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages. The method comprising the following steps. Inspect semiconductor devices on the wafer visually to identify the location of visual defects on dies being manufactured on the wafer and to maintain a count of visual defects on the dies by location. Inspect the semiconductor dies on the wafer to determine the location and number defective dies on the wafer at each of the manufacturing stages. Calculate the defective die count for each stage for the wafer. Calculate the defective bad die count for each stage for the wafer. Determine the percentage of the defective bad die count divided by the defective die count. Plot the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages.