Patents by Inventor Rennie G. Barber

Rennie G. Barber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6943055
    Abstract: A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contaminant sensor may be incorporated into a fabrication device such as a wafer handling device, or can be utilized in the construction of a stand-alone device. An apparatus for detecting contamination on the backside of a semiconductor wafer is also disclosed.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: September 13, 2005
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, George E. Bailey, Rennie G. Barber
  • Patent number: 6898064
    Abstract: A system and method are presented for neutralizing the electric charge binding a semiconductor wafer to an electrostatic chuck. When processing of a semiconductor wafer has been completed, lifter pins, driven by solenoids or pistons, are provided within the chuck to remove the wafer. However, if the electrostatic force has not been completely dissipated, the pins may have to push very hard against the wafer to dislodge it. When this occurs, the wafer may be violently displaced from the chuck, resulting in misplacement of the wafer, or even damage. A system and method are disclosed herein for completely neutralizing the electrostatic charge before removal of the wafer is attempted. Neutralization is detected as the point at which the electrostatic force opposing the lifting mechanism reaches a minimum.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: May 24, 2005
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, Rennie G. Barber
  • Patent number: 6849936
    Abstract: An integrated circuit package comprises a cavity for housing an integrated circuit (IC) and an antenna provided as part of the package that is located substantially outside the cavity. The antenna may be located on the floor of the IC package that lies in the region outside of the IC cavity. Alternatively, the antenna may be located on the upper or lower surface of the lid sealing the IC package. The antenna may be placed in the floor or on a surface of the IC lid by forming depressions in the floor or lid surface and depositing conductive material in the depressions. The conductive material deposition may be by sputtering, evaporation, or other known physical or chemical deposition method. Antennas formed in the upper surface of an IC lid may be coupled to a pin of the IC package so that the antenna may be electrically coupled to a transceiver component on the IC within the package.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: February 1, 2005
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, Rennie G. Barber
  • Patent number: 6837967
    Abstract: A plasma edge cleaning apparatus is configured to remove film deposits from a wafer edge. A gas distribution manifold is annular shaped and positioned to provide plasma process gases near the edge of the wafer. A top insulator and a wafer support each include a magnetic coil to generate a magnetic field for shielding the selected portions of a wafer from the generated plasma. The top insulator is positioned above the wafer during edge processing so as to form a small gap between the top insulator and the wafer to prevent plasma from etching active die areas of the wafer.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: January 4, 2005
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, Steven E. Reder, Rennie G. Barber
  • Publication number: 20040069407
    Abstract: A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contaminant sensor may be incorporated into a fabrication device such as a wafer handling device, or can be utilized in the construction of a stand-alone device. An apparatus for detecting contamination on the backside of a semiconductor wafer is also disclosed.
    Type: Application
    Filed: July 28, 2003
    Publication date: April 15, 2004
    Inventors: Michael J. Berman, George E. Bailey, Rennie G. Barber
  • Publication number: 20030210510
    Abstract: An electrostatic substrate chucking system of the type having an electrostatic chuck for selectively retaining and selectively releasing a substrate. At least one sensor senses at least one parameter that is related to a degree to which electrostatic forces between the electrostatic chuck and the substrate have dissipated. Signals based on the at least one sensed parameter are sent from the sensor to a controller, which receives the signals and determines whether the electrostatic forces between the electrostatic chuck and the substrate have sufficiently dissipated so as to safely remove the substrate from the electrostatic chuck.
    Type: Application
    Filed: May 7, 2002
    Publication date: November 13, 2003
    Inventors: Thomas C. Hann, Jeffrey S. Zola, Rennie G. Barber
  • Patent number: 6627466
    Abstract: A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contaminant sensor may be incorporated into a fabrication device such as a wafer handling device, or can be utilized in the construction of a stand-alone device. An apparatus for detecting contamination on the backside of a semiconductor wafer is also disclosed.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: September 30, 2003
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, George E. Bailey, Rennie G. Barber