Patents by Inventor Renrong Liang
Renrong Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11928752Abstract: A processor device has a CPU cooperating with an input device and an output device, under control of stored instructions, and is arranged to receive service requests at the input device, assign service requests received in successive time periods to respective batches of requests; access stored service provider data to identify available service providers from among a pool of service providers; after completing the assignment of service requests to a batch, perform a matching process to endeavour to match each service request of the batch of requests to a service provider; and for each service provider to whom a match is made, output a notification of the respective potential match from the output device.Type: GrantFiled: September 21, 2022Date of Patent: March 12, 2024Assignee: GRABTAXI HOLDINGS PTE. LTD.Inventors: Kong-Wei Lye, Yang Cao, Swara Desai, Chen Liang, Xiaojia Mu, Yuliang Shen, Sien Y. Tan, Muchen Tang, Renrong Weng, Chang Zhao
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Patent number: 9299566Abstract: A method for forming a germanium-based layer is provided. The method includes: providing a substrate having a Ge or GeSi surface layer; and implanting atoms, molecules, ions or plasmas containing an element Sn into the Ge surface layer to form a Ge-based GeSn layer, or implanting atoms, molecules, ions or plasmas containing an element Sn into the GeSi surface layer to form a Ge-based GeSnSi layer, or co-implanting atoms, molecules, ions or plasmas containing elements Sn and Si into the Ge surface layer to form a Ge-based GeSnSi layer.Type: GrantFiled: March 21, 2014Date of Patent: March 29, 2016Assignee: TSINGHUA UNIVERSITYInventors: Lei Xiao, Jing Wang, Mei Zhao, Renrong Liang, Jun Xu
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Patent number: 9159814Abstract: A memory structure and a method for forming the same are provided. The memory structure comprises: a substrate; a plurality of channel structures formed on the substrate, in which the plurality of channel structures are parallel with each other, each channel structure comprises a plurality of single crystal semiconductor layers and a plurality of oxide layers alternately stacked in a direction perpendicular to the substrate, and at least one of the plurality of oxide layers is a single crystal oxide layer; and a plurality of gate structures matched with the plurality of channel structures, in which each gate structure comprises a gate dielectric layer immediately adjacent to the plurality of channel structures and a gate electrode layer immediately adjacent to the gate dielectric layer.Type: GrantFiled: May 31, 2013Date of Patent: October 13, 2015Assignee: Tsinghua UniversityInventors: Libin Liu, Jing Wang, Renrong Liang
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Publication number: 20150243502Abstract: A method for forming a fin field effect transistor is provided. The method includes: providing a substrate; forming a fin structure with a material Ge or GeSi on the substrate; implanting atoms, molecules, ions or plasmas containing an element Sn into the fin structure with the material Ge or GeSi to form a Ge-based GeSn layer or a Ge-based GeSnSi layer; and forming a gate stack on the Ge-based GeSn layer or the Ge-based GeSnSi layer, the gate stack being oriented transversely to the fin structure.Type: ApplicationFiled: March 18, 2014Publication date: August 27, 2015Inventors: Jing Wang, Lei Xiao, Mei Zhao, Renrong Liang, Jun Xu
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Publication number: 20150243506Abstract: A method for forming a germanium-based layer is provided. The method includes: providing a substrate having a Ge or GeSi surface layer; and implanting atoms, molecules, ions or plasmas containing an element Sn into the Ge surface layer to form a Ge-based GeSn layer, or implanting atoms, molecules, ions or plasmas containing an element Sn into the GeSi surface layer to form a Ge-based GeSnSi layer, or co-implanting atoms, molecules, ions or plasmas containing elements Sn and Si into the Ge surface layer to form a Ge-based GeSnSi layer.Type: ApplicationFiled: March 21, 2014Publication date: August 27, 2015Inventors: Lei Xiao, Jing Wang, Mei Zhao, Renrong Liang, Jun Xu
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Patent number: 9105475Abstract: A method for forming a fin field effect transistor is provided. The method includes: providing a substrate; forming a fin structure with a material Ge or GeSi on the substrate; implanting atoms, molecules, ions or plasmas containing an element Sn into the fin structure with the material Ge or GeSi to form a Ge-based GeSn layer or a Ge-based GeSnSi layer; and forming a gate stack on the Ge-based GeSn layer or the Ge-based GeSnSi layer, the gate stack being oriented transversely to the fin structure.Type: GrantFiled: March 18, 2014Date of Patent: August 11, 2015Assignee: TSINGHUA UNIVERSITYInventors: Jing Wang, Lei Xiao, Mei Zhao, Renrong Liang, Jun Xu
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Patent number: 9105464Abstract: A semiconductor structure with a rare earth oxide is provided. The semiconductor structure comprises: a semiconductor substrate (100); and a plurality of insulation oxide layers (201, 202 . . . 20x) and a plurality of single crystal semiconductor layers (301, 302 . . . 30x) alternately stacked on the semiconductor substrate (100). A material of the insulation oxide layer (201) contacted with the semiconductor substrate (100) is any one of a rare earth oxide, SiO2, SiOxNy and a combination thereof, a material of other insulation oxide layers (202 . . . 20x) is a single crystal rare earth oxide.Type: GrantFiled: December 18, 2012Date of Patent: August 11, 2015Assignee: Tsinghua UniversityInventors: Jing Wang, Renrong Liang, Lei Guo, Jun Xu
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Patent number: 9059268Abstract: A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor comprises: a semiconductor substrate; a channel region formed in the semiconductor substrate, with one or more isolation structures formed in the channel region; a first buried layer and a second buried layer formed in the semiconductor substrate and located at both sides of the channel region respectively, the first buried layer being first type non-heavily-doped, and the second buried layer being second type non-heavily-doped; a source region and a drain region formed in the semiconductor substrate and located on the first buried layer and the second buried layer respectively; and a gate dielectric layer formed on the one or more isolation structures, and a gate formed on the gate dielectric layer.Type: GrantFiled: August 21, 2012Date of Patent: June 16, 2015Assignee: Tsinghua UniversityInventors: Ning Cui, Renrong Liang, Jing Wang, Jun Xu
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Patent number: 9006088Abstract: A method for forming a semiconductor gate structure and a semiconductor gate structure are provided. The method includes: providing a substrate with a Ge layer as a surface thereof; forming a Sn layer on the Ge layer, in which an interface between the Ge layer and the Sn layer is a GeSn layer; removing the Sn layer to expose the GeSn layer; forming a GeSnOx passivation layer by performing an oxidation treatment for the GeSn layer, or forming a GeSnN or GeSnON passivation layer by performing a passivation treatment for the GeSn layer; and forming a gate stack on the GeSnOx , GeSnN or GeSnON passivation layer.Type: GrantFiled: June 14, 2013Date of Patent: April 14, 2015Assignee: Tsinghua UniversityInventors: Mei Zhao, Renrong Liang, Jing Wang, Jun Xu
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Patent number: 8963295Abstract: A semiconductor structure with beryllium oxide is provided. The semiconductor structure comprises: a semiconductor substrate (100); and a plurality of insulation oxide layers (201, 202 . . . 20x) and a plurality of single crystal semiconductor layers (301, 302 . . . 30x) alternately stacked on the semiconductor substrate (100). A material of the insulation oxide layer (201) contacted with the semiconductor substrate (100) is any one of beryllium oxide, SiO2, SiOxNy and a combination thereof, a material of other insulation oxide layers (202 . . . 20x) is single crystal beryllium oxide.Type: GrantFiled: December 18, 2012Date of Patent: February 24, 2015Assignee: Tsinghua UniversityInventors: Jing Wang, Renrong Liang, Lei Guo, Jun Xu
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Patent number: 8927966Abstract: A dynamic random access memory unit and a method for fabricating the same are provided. The dynamic random access memory unit comprises: a substrate; an insulating buried layer formed on the substrate; a body region formed on the insulating buried layer and used as a charge storing region; two isolation regions formed on the body region, in which a semiconductor contact region is formed between the isolation regions and is a charge channel; a source, a drain and a channel region formed on the isolation regions and the semiconductor contact region respectively and constituting a transistor operating region which is partially separated from the charge storing region by the isolation regions and connected with the charge storing region via the charge channel; a gate dielectric layer formed on the transistor operating region, a gate formed on the gate dielectric layer; a source metal contact layer, a drain metal contact layer.Type: GrantFiled: October 18, 2012Date of Patent: January 6, 2015Assignee: Tsinghua UniversityInventors: Libin Liu, Renrong Liang, Jing Wang, Jun Xu
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Publication number: 20150001623Abstract: A field effect transistor and a method for forming the same are provided. The field effect transistor comprises: a substrate (100); an ultra-thin insulator layer (200) formed on the substrate (100), wherein a material of the ultra-thin insulator layer (200) is a monocrystalline rare earth oxide or a monocrystalline beryllium oxide; an ultra-thin semiconductor monocrystalline film (300) formed on the ultra-thin insulator layer (200); and a gate stack (400) formed on the ultra-thin semiconductor monocrystalline film (300), and comprising a gate dielectric (410) and a gate electrode (420) formed on the gate dielectric (410).Type: ApplicationFiled: August 20, 2013Publication date: January 1, 2015Applicant: TSINGHUA UNIVERSITYInventors: Jing Wang, Renrong Liang, Jun Xu
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Patent number: 8860143Abstract: A semiconductor structure is provided. The semiconductor structure comprises: a substrate; a gate dielectric layer formed on the substrate; a metal gate electrode layer formed on the gate dielectric layer; and at least one metal-containing adjusting layer for adjusting a work function of the semiconductor structure, in which an interfacial layer is formed between the substrate and the gate dielectric layer, and an energy of bond between a metal atom in the metal-containing adjusting layer and an oxygen atom is larger than that between an atom of materials forming the gate dielectric layer or the interfacial layer and an oxygen atom. Further, a method for forming the semiconductor structure is also provided.Type: GrantFiled: August 2, 2011Date of Patent: October 14, 2014Assignee: Tsinghua UniversityInventors: Mei Zhao, Renrong Liang, Jing Wang, Jun Xu
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Patent number: 8860140Abstract: The present disclosure provides a TFET, which comprises: a substrate; a channel region formed in the substrate, and a source region and a drain region formed on two sides of the channel region; a gate stack formed on the channel region, wherein the gate stack comprises: a gate dielectric layer, and at least a first gate electrode and a second gate electrode distributed in a direction from the source region to the drain region and formed on the gate dielectric layer, and the first gate electrode and the second gate electrode have different work functions; and a first side wall and a second side wall formed on a side of the first gate electrode and on a side of the second gate electrode respectively.Type: GrantFiled: June 24, 2011Date of Patent: October 14, 2014Assignee: Tsinghua UniversityInventors: Renrong Liang, Ning Cui, Jing Wang, Jun Xu
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Patent number: 8853674Abstract: A tunneling field effect transistor structure and a method for forming the same are provided. The tunneling field effect transistor structure comprises: a substrate; a plurality of convex structures formed on the substrate, every two adjacent convex structures being separated by a predetermined cavity less than 30 nm in width, the convex structures comprising a plurality of sets, and each set comprising more than two convex structures; a plurality of floated films formed on tops of the convex structures, each floated film corresponding to one set of convex structures, a region of each floated film corresponding to a top of an intermediate convex structure in each set being formed as a channel region, and regions of the each floated film at both sides of the channel region are formed as a source region and a drain region with opposite conductivity types respectively; and a gate stack formed on each channel region.Type: GrantFiled: August 28, 2012Date of Patent: October 7, 2014Assignee: Tsinghua UniversityInventors: Ning Cui, Renrong Liang, Jing Wang, Jun Xu
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Publication number: 20140291752Abstract: A memory structure and a method for forming the same are provided. The memory structure comprises: a substrate; a plurality of channel structures formed on the substrate, in which the plurality of channel structures are parallel with each other, each channel structure comprises a plurality of single crystal semiconductor layers and a plurality of oxide layers alternately stacked in a direction perpendicular to the substrate, and at least one of the plurality of oxide layers is a single crystal oxide layer; and a plurality of gate structures matched with the plurality of channel structures, in which each gate structure comprises a gate dielectric layer immediately adjacent to the plurality of channel structures and a gate electrode layer immediately adjacent to the gate dielectric layer.Type: ApplicationFiled: May 31, 2013Publication date: October 2, 2014Applicant: TSINGHUA UNIVERSITYInventors: Libin Liu, Jing Wang, Renrong Liang
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Publication number: 20140291727Abstract: A method for forming a semiconductor gate structure and a semiconductor gate structure are provided. The method includes: providing a substrate with a Ge layer as a surface thereof; forming a Sn layer on the Ge layer, in which an interface between the Ge layer and the Sn layer is a GeSn layer; removing the Sn layer to expose the GeSn layer; forming a GeSnOx passivation layer by performing an oxidation treatment for the GeSn layer, or forming a GeSnN or GeSnON passivation layer by performing a passivation treatment for the GeSn layer; and forming a gate stack on the GeSnOx, GeSnN or GeSnON passivation layer.Type: ApplicationFiled: June 14, 2013Publication date: October 2, 2014Applicant: Tsinghua UniversityInventors: Mei Zhao, Renrong Liang, Jing Wang, Jun Xu
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Patent number: 8815690Abstract: The present disclosure provides a tunneling device, which comprises: a substrate; a channel region formed in the substrate, and a source region and a drain region formed on two sides of the channel region; and a gate stack formed on the channel region and a first side wall and a second side wall formed on two sides of the gate stack, wherein the gate stack comprises: a first gate dielectric layer; at least a first gate electrode and a second gate electrode formed on the first gate dielectric layer; a second gate dielectric layer formed between the first gate electrode and the first side wall; and a third gate dielectric layer formed between the second gate electrode and the second side wall.Type: GrantFiled: June 24, 2011Date of Patent: August 26, 2014Assignee: Tsinghua UniversityInventors: Ning Cui, Renrong Liang, Jing Wang, Jun Xu
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Patent number: 8803225Abstract: A tunneling field effect transistor and a method for fabricating the same are provided. The tunneling field effect transistor includes: a semiconductor substrate and a drain layer formed in the semiconductor substrate, in which the drain layer is first type heavily doped; an epitaxial layer formed on the drain layer, with an isolation region formed in the epitaxial layer; a buried layer formed in the epitaxial layer, in which the buried layer is second type lightly doped; a source formed in the buried layer, in which the source is second type heavily doped; a gate dielectric layer formed on the epitaxial layer, and a gate formed on the gate dielectric layer; and a source metal contact layer formed on the source, and a drain metal contact layer formed under the drain layer.Type: GrantFiled: September 6, 2012Date of Patent: August 12, 2014Assignee: Tsinghua UniversityInventors: Ning Cui, Renrong Liang, Jing Wang, Jun Xu
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Patent number: 8785938Abstract: A method for forming a polycrystalline film, a polycrystalline film formed by the method and a thin film transistor fabricated from the polycrystalline film are provided. The method comprises the steps of: providing a substrate; forming a thermal conductor layer on the substrate; etching the thermal conductor layer until the substrate is exposed to form a thermal conductor pattern; forming a seed layer on the thermal conductor layer and the substrate; etching the seed layer to form seed crystals on both sidewalls of the thermal conductor; forming an amorphous layer on the substrate, the thermal conductor layer and the seed crystals; etching the amorphous layer; and recrystallizing the amorphous layer to form a polycrystalline layer.Type: GrantFiled: August 2, 2012Date of Patent: July 22, 2014Assignee: Tsinghua UniversityInventors: Lianfeng Zhao, Renrong Liang, Mei Zhao, Jing Wang, Jun Xu