Patents by Inventor Renu Rawat

Renu Rawat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory with a controllable I/O functional unit
    Patent number: 10861575
    Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: December 8, 2020
    Assignee: Arm Limited
    Inventors: Rajiv Kumar Sisodia, Renu Rawat, Paul Darren Hoxey, Vikash, Kumaraswamy Ramanathan, Sanjay Mangal, Yew Keong Chong
  • Memory with a Controllable I/O Functional Unit
    Publication number: 20200066365
    Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 27, 2020
    Inventors: Rajiv Kumar Sisodia, Renu Rawat, Paul Darren Hoxey, Vikash, Kumaraswamy Ramanathan, Sanjay Mangal, Yew Keong Chong
  • Memory with a controllable I/O functional unit
    Patent number: 10460822
    Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: October 29, 2019
    Assignee: ARM Limited
    Inventors: Rajiv Kumar Sisodia, Renu Rawat, Paul Darren Hoxey, Vikash, Kumaraswamy Ramanathan, Sanjay Mangal, Yew Keong Chong
  • Memory with a Controllable I/O Functional Unit
    Publication number: 20190066814
    Abstract: A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 28, 2019
    Inventors: Rajiv Kumar Sisodia, Renu Rawat, Paul Darren Hoxey, Vikash, Kumaraswamy Ramanathan, Sanjay Mangal, Yew Keong Chong