Abstract: According to an aspect of the disclosure, a computational processing method of multiplier, performed by a processor chip, includes: obtaining, based on n first operands a[k], a first operating part A including BIT(A) bits; obtaining x first encoded data Enc[m] by assigning a lowest bit of consecutive three-bit numbers spanning two adjacent first operands a[k] and a[k?1] to 0, and performing Booth-encoding on the first operating part A; obtaining, based on n second operands b[k], n corresponding second operating parts B[k], each of which has BIT(B) bits; obtaining x partial products based on multiplying the x first encoded data Enc[m] with the n corresponding second operating parts; obtaining an accumulation result based on accumulating the x partial products; obtaining a multiplication result based on truncating the accumulation result; wherein, n, k, x, and m are integers, and wherein 0?k<n, and 0?m<x.

Abstract: An execution method for instruction conflict, includes: obtaining instructions to be executed in waves; determining whether a first instruction of a first wave meets one or more instruction emission conditions; determining, based on the first instruction meeting the one or more instruction emission conditions, a type of the of the first instruction; issuing, based on the type being a second type, the first instruction to be executed; and executing an operation of the first instruction.

Abstract: The present application relates to a data processing method, a computer device, and a storage medium. The method includes: acquiring data formats of two pieces of input data; the data formats of the two pieces of input data being the same; determining a target data conversion algorithm matching the data formats from a plurality of preset data conversion algorithms, and performing, by using the target data conversion algorithm, data format conversion on the two pieces of input data to obtain at least two pieces of target input data; processing, by using a multiplier, the at least two pieces of target input data to obtain a preliminary operation result; and determining truncation bit widths corresponding to the two pieces of input data, and processing the preliminary operation result according to the truncation bit widths, to obtain a multiplication operation result corresponding to the two pieces of input data.

Abstract: Multiplication-accumulation method and apparatus, a processor, and a computer program product are provided.

Abstract: Convolution operation method and apparatus, matrix decompression device and graphics processor are provided. The method includes: loading, from a preset memory layout, at least one target feature tile constituting any sub-feature map in an original feature map for the any sub-feature map; the memory layout being obtained by writing at least one feature tile into memory according to preset way of data arrangement; the at least one feature tile being obtained by tiling the original feature map; decompressing a feature map which is composed of the at least one target feature tile according to a convolution parameter of a convolutional layer to obtain a destination decompressed matrix; performing a matrix multiplication operation on the destination decompressed matrix and the decompressed matrix corresponding to a convolution kernel to obtain a convolution operation result of the original feature map. The present disclosure may improve the convolution operation efficiency.

Abstract: An apparatus integrates arithmetic with logic operations. The apparatus includes a calculation device that calculates source data to generate and output first destination data. The apparatus further includes a normalization unit, coupled to the calculation device, that normalizes the first destination data to generate second destination data of a first type when receiving a signal indicating an output of first-type data, and normalizing the first destination data to generate the second destination data of a second type when receiving the signal indicating an output of second-type data.

Abstract: An apparatus integrates arithmetic with logic operations. The apparatus includes a calculation device that calculates source data to generate and output first destination data. The apparatus further includes a normalization unit, coupled to the calculation device, that normalizes the first destination data to generate second destination data of a first type when receiving a signal indicating an output of first-type data, and normalizing the first destination data to generate the second destination data of a second type when receiving the signal indicating an output of second-type data.

Abstract: An apparatus for integrating arithmetic with logic operations contains at least a calculation device and a post-logic unit. The calculation device calculates source data to generate and output first destination data. The post-logic unit, coupled to the calculation device, performs a comparison operation for comparing the first destination data with 0 and outputs a comparison result.

Abstract: A method for calculating FP (Full Precision) and PP (Partial Precision) values, performed by an ID (Instruction Decode) unit, contains at least the following steps: decoding an instruction request from a compiler; executing a loop m times to generate m microinstructions for calculating first-type data, or n times to generate n microinstructions for calculating second-type data according to the instruction mode of the instruction request, thereby enabling ALGs (Arithmetic Logic Groups) to execute lanes of a thread. m is less than n and the precision of the first-type data is lower than the precision of the second-type data.

Abstract: An apparatus for integrating arithmetic with logic operations contains at least a calculation device and a post-logic unit. The calculation device calculates source data to generate and output first destination data. The post-logic unit, coupled to the calculation device, performs a comparison operation for comparing the first destination data with 0 and outputs a comparison result.

Abstract: A method for calculating FP (Full Precision) and PP (Partial Precision) values, performed by an ID (Instruction Decode) unit, contains at least the following steps: decoding an instruction request from a compiler; executing a loop m times to generate m microinstructions for calculating first-type data, or n times to generate n microinstructions for calculating second-type data according to the instruction mode of the instruction request, thereby enabling ALGs (Arithmetic Logic Groups) to execute lanes of a thread. m is less than n and the precision of the first-type data is lower than the precision of the second-type data.