Patents by Inventor Reo Yamamoto

Reo Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11859312
    Abstract: Provided are a method of cleaning a group III nitride single crystal substrate which enables the roughness of a nitrogen-polar face of the group III nitride single crystal substrate to be suppressed to remove foreign substances, and a method of producing a group III nitride single crystal substrate. The method of cleaning a group III nitride single crystal substrate having a group III element-polar face, and the nitrogen-polar face opposite the group III element-polar face includes: cleaning the nitrogen-polar face with a detergent including a fluoroorganic compound.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: January 2, 2024
    Assignee: TOKUYAMA CORPORATION
    Inventors: Masayuki Fukuda, Reo Yamamoto
  • Publication number: 20230313413
    Abstract: Provided are a method of cleaning a group III nitride single crystal substrate which enables the roughness of a nitrogen-polar face of the group III nitride single crystal substrate to be suppressed to remove foreign substances, and a method of producing a group III nitride single crystal substrate. The method of cleaning a group III nitride single crystal substrate having a group III element-polar face, and the nitrogen-polar face opposite the group III element-polar face includes: cleaning the nitrogen-polar face with a detergent including a fluoroorganic compound.
    Type: Application
    Filed: August 17, 2022
    Publication date: October 5, 2023
    Applicant: TOKUYAMA CORPORATION
    Inventors: Masayuki FUKUDA, Reo YAMAMOTO
  • Publication number: 20170296690
    Abstract: To provide an ultraviolet sterilizing apparatus that is capable of efficiently performing ultraviolet sterilization on a large volume of gas or pressurized liquid in a short time, can be made compact, and can be stably and safely used for a long time.
    Type: Application
    Filed: September 3, 2015
    Publication date: October 19, 2017
    Inventors: Shingo MATSUI, Yuriko HORII, Reo YAMAMOTO, Keiichiro HIRONAKA, Yasutaka HAMA
  • Patent number: 7459794
    Abstract: A substrate for device bonding includes a substrate having an electrode layer and a solder layer formed on the electrode layer, wherein the solder layer is a Pb-free solder layer which comprises (1) a base metal composed of (i) Sn, (ii) Sn and Au, or (iii) In, (2) at least one metal selected from the group consisting of Bi, In (only in the case where the base metal is Sn, or Sn and Au), Zn, Au (only in the case where the base metal is In) and Sb, and (3) at least one metal selected from the group consisting of Ag, Ni, Fe, Al, Cu and Pt, and the solder layer has a thickness of 1 to 15 ?m and a surface roughness (Ra) of not more than 0.11 ?m.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: December 2, 2008
    Assignee: Tokuyama Corporation
    Inventors: Hiroki Yokoyama, Yasuko Takeda, Reo Yamamoto
  • Publication number: 20070001315
    Abstract: A substrate for device bonding includes a substrate having an electrode layer and a solder layer formed on the electrode layer, wherein the solder layer is a Pb-free solder layer which comprises (1) a base metal composed of (i) Sn, (ii) Sn and Au, or (iii) In, (2) at least one metal selected from the group consisting of Bi, In (only in the case where the base metal is Sn, or Sn and Au), Zn, Au (only in the case where the base metal is In) and Sb, and (3) at least one metal selected from the group consisting of Ag, Ni, Fe, Al, Cu and Pt, and the solder layer has a thickness of 1 to 15 ?m and a surface roughness (Ra) of not more than 0.11 ?m.
    Type: Application
    Filed: August 17, 2004
    Publication date: January 4, 2007
    Applicant: TOKUYAMA CORPORATION
    Inventors: Hiroki Yokoyama, Yasuko Takeda, Reo Yamamoto
  • Patent number: 6762496
    Abstract: A sintered aluminum nitride substrate which has a via hole and an internal electrically conductive layer, having high thermal conductivity and high adhesion strength between the sintered aluminum nitride substrate and the internal electrically conductive layer or the via hole and having other excellent properties. The substrate comprising an internal electrically conductive layer, at least one electrically conductive via hole formed between the internal electrically conductive layer and at least one surface of the substrate, wherein the thermal conductivity of the aluminum nitride sintering product at 25° C. is 190 W/mK or more, and the adhesion strength between the aluminum nitride sintering product and the internal electrically conductive layer is 5.0 kg/mm2 or more.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: July 13, 2004
    Assignee: Tokuyama Corporation
    Inventors: Reo Yamamoto, Yoshihide Kamiyama, Yuichiro Minabe
  • Patent number: 6733822
    Abstract: A sintered aluminum nitride having satisfactorily densified via holes, which is free from cracking and has an excellent appearance, is produced through firing an aluminum nitride molding having at least one highly isolated through-hole for via hole formation. At least one through-hole for formation of dummy via holes not used for electrical connection is formed around the highly isolated through-hole for via hole formation, and the through-hole for dummy via hole formation is also filled with a conductive paste. Thereafter, the aluminum nitride molding is fired into the sintered aluminum nitride.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: May 11, 2004
    Assignee: Tokuyama Corporation
    Inventors: Reo Yamamoto, Yoshihide Kamiyama
  • Publication number: 20040016570
    Abstract: It is an object to provide a method of efficiently manufacturing a double-sided circuit board having a metallic via hole which can suitably be used as a submount for mounting a semiconductor device, that is, a substrate in which the electrical contact of a metallic via hole and a circuit pattern is excellent and an element can easily be bonded and positioned. In a ceramic substrate having a via hole filled with a conductive material, a ceramic portion of at least one of faces of the ceramic substrate has a surface roughness of Ra≦0.8 &mgr;m, a substrate in which the conductive material filled in the via hole present on at least one of the faces is protruded from a surface of the face with a height of 0.3 to 5.
    Type: Application
    Filed: June 10, 2003
    Publication date: January 29, 2004
    Inventors: Reo Yamamoto, Yoshihide Yamamoto
  • Publication number: 20030108729
    Abstract: The object of the present invention is to provide a sintered aluminum nitride substrate which has a via hole and an internal electrically conductive layer, having high thermal conductivity and high adhesion strength between the sintered aluminum nitride substrate and the internal electrically conductive layer or the via hole and having other excellent properties. The substrate according to the invention comprising an internal electrically conductive layer, at least one electrically conductive via hole formed between the internal electrically conductive layer and at least one surface of the substrate, wherein the thermal conductivity of the aluminum nitride sintering product at 25° C. is 190 W/mK or more, and the adhesion strength between the aluminum nitride sintering product and the internal electrically conductive layer is 5.0 kg/mm2 or more.
    Type: Application
    Filed: July 26, 2002
    Publication date: June 12, 2003
    Inventors: Reo Yamamoto, Yoshihide Kamiyama, Yuichiro Minabe
  • Patent number: 6475924
    Abstract: The present invention produces the following substrate and the following process for producing the substrate. A substrate obtained by filling through holes in a sintered product of aluminum nitride with an electrically conducting layer, wherein said sintered product of aluminum nitride has a thermal conductivity of not smaller than 190 W/mK, and the adhesion strength between said sintered product of aluminum nitride and said electrically conducting layer is not smaller than 5.0 kg/mm2.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: November 5, 2002
    Assignee: Tokuyama Corporation
    Inventors: Reo Yamamoto, Yoshihiko Numata, Yuichiro Minabe, Mitsutoshi Hikasa
  • Publication number: 20020160903
    Abstract: A sintered aluminum nitride having satisfactorily densified via holes, which is free from cracking and has excellent appearance, is produced through firing an aluminum nitride molding having at least one highly isolated through-hole for via hole formation. At least one through-hole for formation of dummy via holes not used for electrical connection is formed around the highly isolated through-hole for via hole formation, and the through-hole for dummy via hole formation is also filled with a conductive paste. Thereafter, the aluminum nitride molding is fired into the sintered aluminum nitride.
    Type: Application
    Filed: February 6, 2002
    Publication date: October 31, 2002
    Inventors: Reo Yamamoto, Yoshihide Kamiyama
  • Publication number: 20010036506
    Abstract: The present invention prodices the following substrate and the following process for producing the substrate. A substrate obtained by filling through holes in a sintered product of aluminum nitride with an electrically conducting layer, wherein said sintered product of aluminum nitride has a thermal conductivity of not smaller than 190 W/mK, and the adhesion strength between said sintered product of aluminum nitride and said electrically conducting layer is not smaller than 5.0 kg/mm2.
    Type: Application
    Filed: April 18, 2001
    Publication date: November 1, 2001
    Inventors: Reo Yamamoto, Yoshihiko Numata, Yuichiro Minabe, Mitsutoshi Hikasa
  • Patent number: 5770821
    Abstract: A submount including:an insulating substrate having therein a throughhole filled with a sintered metal powder, andan electroconductive layer formed on each of the two opposing surfaces of the insulating substrate, wherein the sintered metal powder filled in the throughhole of the insulating substrate is formed, for example, by filling, in the throughhole, a metal paste composed mainly of copper, tungsten, molybdenum or the like and then conducting firing and wherein the two electroconductive layers are electrically connected with each other at least partially by the sintered metal powder. The submount according to the present invention has a low electric resistance and high reliability and can be made in a small size. Therefore, it can be suitably used as a novel submount for semiconductor laser element, which promises electrical conduction between a semiconductor laser element and a heat sink.
    Type: Grant
    Filed: July 12, 1996
    Date of Patent: June 23, 1998
    Assignee: Tokuyama Corporation
    Inventors: Mitsutoshi Hikasa, Yoshihiko Numata, Reo Yamamoto