Abstract: A test system is disclosed wherein a device under test (DUT) includes a trace logic analyzer (TLA) that receives and stores test data. The test system includes both a master tester and a slave tester. The slave tester operates at a high speed data rate substantially faster than that of the master tester. The master tester instructs the TLA to monitor data that the DUT receives from the slave tester to detect a predetermined data pattern within the data. The slave tester transmits data including the predetermined data pattern to the DUT. The DUT receives the data. When the TLA in the DUT detects the predetermined data pattern in the received data, the TLA stores that data pattern as a stored data pattern. The master tester retrieves the stored data pattern and compares the stored data pattern with the original predetermined data pattern. If the master tester determines that the stored data pattern is the same as the original predetermined data pattern, then the master tester generates a pass result.

Abstract: A test system is disclosed wherein a device under test (DUT) includes a trace logic analyzer (TLA) that receives and stores test data. The test system includes both a master tester and a slave tester. The slave tester operates at a high speed data rate substantially faster than that of the master tester. The master tester instructs the TLA to monitor data that the DUT receives from the slave tester to detect a predetermined data pattern within the data. The slave tester transmits data including the predetermined data pattern to the DUT. The DUT receives the data. When the TLA in the DUT detects the predetermined data pattern in the received data, the TLA stores that data pattern as a stored data pattern. The master tester retrieves the stored data pattern and compares the stored data pattern with the original predetermined data pattern. If the master tester determines that the stored data pattern is the same as the original predetermined data pattern, then the master tester generates a pass result.

Abstract: In one form of the invention, an apparatus has a first switch operable in an error injection state for interrupting a transfer of first data from a memory device to a test system, and in a normal state for permitting unimpeded data transfer. The apparatus has a second switch operable in an error injection state for sending second data to the test system instead of corresponding bits of the first data. Logic circuitry of the apparatus reads the first data and controls an error injection sequence that includes switching the first and second switches from their respective normal states to their respective error injection states responsive to receiving the command. The apparatus determines whether at least one of the corresponding data bits of the first and second data have disparate logic states independently of switching the first and second switches back to their respective normal states.