Abstract: A method, non-transitory computer readable medium, and apparatus for performing fault injection and verification on an integrated circuit are disclosed. For example, the method generates a mask file for one or more modules of a hierarchical design, wherein the mask file identifies one or more essential bits, receives a selection of one of the one or more modules as a selected module for the fault injection and the verification to be applied, performs the fault injection on at least one essential bit of the selected module based upon the mask file for the selected module, and performs the verification on the selected module.

Abstract: A method, non-transitory computer readable medium, and apparatus for performing single event upset detection and correction are disclosed. For example, the method comprises: setting, by a processor, at least one starting address for each of a plurality of rows of a design for an integrated circuit, setting, by the processor, at least one ending address for each of the plurality of rows of the design, and performing, by the processor, the single event upset detection and correction scan in parallel, from the at least one starting address for each of the plurality of rows to the at least one ending address for each of the plurality of rows.

Abstract: Methods of generating a PLD design implementation according to a design architecture tailored to specified requirements. A hardware description language (HDL) description for the PLD design includes at least one parameter value for the PLD design that will affect the preferred implementation of the design. This parameter value is passed to a high-level language (HLL) function, which is used to determine a tailored design architecture in accordance with the specified needs of the target application. The HLL function returns data specifying the tailored design architecture. This data is used in generating an implementation of the PLD design that follows the constraints imposed by the tailored design architecture. The result can be, for example, a logic gate representation of the PLD design, a netlist of the design, or a bitstream implementing the design in a target PLD.