Patents by Inventor Reuben A. Aspacio

Reuben A. Aspacio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Enhanced glitch removal circuit
    Patent number: 6249141
    Abstract: An enhanced glitch eater circuit for eliminating glitch signals occurring within a predetermined period from a raising edge or a falling edge of a signal pulse is comprised of an inverter connected to a transmission gate which is controlled by a two-input XNOR (exclusive-NOR) gate receiving a latched signal at one input and a delay latched signal at the other input, the latched signal being from the output of the transmission gate. The latched signal may be reset by a transistor.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: June 19, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Reuben A. Aspacio, Rajesh Bharadwaj, Hieu Xuan Nguyen
  • Enhanced glitch removal circuit
    Patent number: 6134252
    Abstract: An enhanced glitch eater circuit for eliminating glitch signals occurring within a predetermined period from a raising edge or a falling edge of a signal pulse is comprised of an inverter connected to a transmission gate which is controlled by a two-input XNOR (exclusive-NOR) gate receiving a latched signal at one input and a delay latched signal at the other input, the latched signal being from the output of the transmission gate. The latched signal may be reset by a transistor.
    Type: Grant
    Filed: April 11, 1997
    Date of Patent: October 17, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Reuben A. Aspacio, Rajesh Bharadwaj, Hieu Xuan Nguyen
  • Low power register memory element circuits
    Patent number: 5793672
    Abstract: A flip-flop for storing a bit of digital information generally used in register architectures is comprised of a two-input NAND gate and a D-type flip-flop. The output of the NAND gate is connected to the clock terminal of the flip-flop and the data signal is directed to the data terminal of the flip-flop. A new clock scheme is provided with for this circuit configuration in order to properly store the data signal.
    Type: Grant
    Filed: March 11, 1997
    Date of Patent: August 11, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jacques Ah Miow Wong, Reuben A. Aspacio, Beng Chew Khou