Abstract: The present invention relates to a fuel cell humidifier which can prevent condensate water from entering a running fuel cell stack. A fuel cell humidifier according to an embodiment of the present invention comprises: a humidification module; a first cap having an air discharge port for supplying air humidified by the humidification; a second cap having an air inlet port for receiving the air supplied from the outside; a bypass tube for transferring condensate water, which is generated in the interior space of the first cap or flows into the interior space of the first cap from the hollow fiber membranes, to the interior space of the housing where the off-gas flows; and a condensation inducing part extending from the air discharge port to expand the humidified air so as to induce condensation of condensate water while slowing down the speed thereof.

Abstract: The present invention relates to a fuel cell system capable of adjusting a bypass flow rate, in which the bypass flow rate can be automatically adjusted according to the temperature of an exhaust gas discharged from a fuel cell stack. The fuel cell system capable of adjusting a bypass flow rate, according to an embodiment of the present invention, comprises: an exhaust gas inlet flow path; an exhaust gas discharge flow path; a bypass flow path for bypassing a membrane humidifier to allow at least a portion of an exhaust gas discharged from a fuel cell stack to flow to the exhaust gas discharge flow path; and a bypass flow rate control unit that is formed in the bypass flow path and adjusts the opening degree of the bypass flow path according to the temperature of the exhaust gas discharged from the fuel cell stack.

Abstract: The present invention relates to a membrane humidifier for a fuel cell, which can prevent a decrease in humidification efficiency, caused by a pressure difference between the inside and the outside of the membrane humidifier. The membrane humidifier for a fuel cell, according to an embodiment of the present invention, comprises: a middle case having a module insertion part formed therein; a cap case coupled to the middle case; a hollow fiber membrane module inserted in the module insertion part; and an active pressure buffer part formed between the middle case and the module insertion part to prevent expansion of the module insertion part due to a pressure difference between the inside and the outside of the middle case or relieve the pressure difference according to output states of the fuel cell.

Abstract: The present invention relates to a fuel cell membrane humidifier capable of preventing a humidification efficiency decrease caused by the pressure difference between the inside and the outside of the membrane humidifier. The fuel cell membrane humidifier according to an embodiment of the present invention comprises: a middle case in which a module insertion part, including an outer partition wall formed spaced apart from an inner wall of the middle case, is formed; a cap case coupled to the middle case; a hollow fiber membrane module inserted into the module insertion part; and an active pressure buffer part that is formed between the middle case and the module insertion part and prevents the module insertion part from expanding due to the pressure difference between the inside and the outside of the middle case, or resolves the pressure difference, according to the output status of the fuel cell.

Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

Abstract: In a method of operating a memory device, a first command to allow the memory device to enter an idle mode is received. A reference time interval is adjusted based on process, voltage and temperature (PVT) variation associated with the memory device. The reference time interval is used to determine a start time point of a power control operation for reducing power consumption of the memory device. A first time interval during which the idle mode is maintained is internally measured based on the first command. The power control operation is performed in response to the first time interval being longer than the reference time interval.

Abstract: The present invention relates to an apparatus and a method of folding a pouch case of a battery cell, and more particularly, to an apparatus and a method of folding a pouch case of a battery cell capable of preventing a meandering in a folding process and reducing non-uniformity of a folding amount by forming a pre-folding line on a pouch wing and folding the pouch wing on the basis of the pre-folding line.

Abstract: The present invention relates to an apparatus and a method of folding a pouch case of a battery cell, and more particularly, to an apparatus and a method of folding a pouch case of a battery cell capable of preventing a meandering in a folding process and reducing non-uniformity of a folding amount by forming a pre-folding line on a pouch wing and folding the pouch wing on the basis of the pre-folding line.

Abstract: A semiconductor memory device includes a memory cell array, a row decoder and a timing/voltage control circuit. The memory cell array is divided into a plurality of row blocks by one or more row block identity bits, and each of the of row blocks includes sub-array blocks arranged in a first direction. A row address includes the one or more row block identity bits. The row decoder activates a first word-line coupled to a first memory cell, activates a second word-line coupled to a second memory cell in response to the row address, and outputs a row block information signal. The timing/voltage control circuit adjusts at least one of an operation interval and an operation voltage of a memory operation on the first memory cell and the second memory cell according to a distance in a second direction crossing the first direction from a reference position, based on the row block information signal.

Abstract: The present invention relates to an apparatus and a method of folding a pouch case of a battery cell, and more particularly, to an apparatus and a method of folding a pouch case of a battery cell capable of preventing a meandering in a folding process and reducing non-uniformity of a folding amount by forming a pre-folding line on a pouch wing and folding the pouch wing on the basis of the pre-folding line.

Abstract: According to some embodiments, for a memory device including a base die and a stack of memory dies including a plurality of memory dies stacked on the base die, the base die including a plurality of first input/output (i/o) terminals that are command/address and data terminals and a plurality of second i/o terminals that are direct access terminals, a method includes receiving at the plurality of first i/o terminals a command/address, a clock signal, and data; first transmitting the command/address, clock signal, and data received by the plurality of first i/o terminals from the base die to the stack of memory dies; and second transmitting at least part of one or more of the command/address, clock signal, and data received by a set of the plurality of first i/o terminals through a circuit of the base die to the plurality of second i/o terminals.

Abstract: A semiconductor memory device includes an interface semiconductor die, at least one memory semiconductor die, and through-silicon vias connecting the interface semiconductor die and the memory semiconductor die. The interface semiconductor die includes command pins to receive command signals transferred from a memory controller and an interface command decoder to decode the command signals. The memory semiconductor die includes a memory integrated circuit configured to store data and a memory command decoder to decode the command signals transferred from the interface semiconductor die. The interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller. The interface and memory command decoders generate interface and memory clock enable signals to control clock supply with respect to the interface and memory semiconductor dies based on a power mode command transferred through the plurality of command pins from the memory controller.

Abstract: In a method of operating a memory device, a first command to allow the memory device to enter an idle mode is received. A reference time interval is adjusted based on process, voltage and temperature (PVT) variation associated with the memory device. The reference time interval is used to determine a start time point of a power control operation for reducing power consumption of the memory device. A first time interval during which the idle mode is maintained is internally measured based on the first command. The power control operation is performed in response to the first time interval being longer than the reference time interval.

Abstract: A semiconductor device includes a cell area in which a plurality of memory cells are arranged in an array structure, and a peripheral area in which circuits configured to drive the memory cells are arranged, the peripheral area being next to the cell area. The cell area is divided into a plurality of banks, and the plurality of banks comprise first banks having a base size and second banks having a size of 1/(2*n) (wherein n is an integer greater than or equal to 1) of the base size. The plurality of banks are arranged in a first direction and a second direction perpendicular to the first direction, and the semiconductor device has a shape of a rectangular chip which is elongated in the second direction.

Abstract: An apparatus for identifying a warship receives a warship image, estimates a photographing angle and a photographing altitude of the warship from the real warship image, generates virtual warship images from stored virtual warship models based on the estimated photographing angle and photographing altitude, generates virtual warship part images in which main parts are classified and displayed for each of the virtual warship images, generates a part segmentation image in which main parts are classified and displayed for the real warship image, and outputs a type and class identification result of the warship by calculating similarity between each virtual warship part image and the part segmentation image.

Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.

Abstract: According to some embodiments, for a memory device including a base die and a stack of memory dies including a plurality of memory dies stacked on the base die, the base die including a plurality of first input/output (i/o) terminals that are command/address and data terminals and a plurality of second i/o terminals that are direct access terminals, a method includes receiving at the plurality of first i/o terminals a command/address, a clock signal, and data; first transmitting the command/address, clock signal, and data received by the plurality of first i/o terminals from the base die to the stack of memory dies; and second transmitting at least part of one or more of the command/address, clock signal, and data received by a set of the plurality of first i/o terminals through a circuit of the base die to the plurality of second i/o terminals.

Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit.