Abstract: A clock generator is disclosed that includes a lock detector. The lock detector is configured to generate a lock signal based on control signals of a phase lock loop circuit that generates an output clock of a desired frequency that is phase locked to a reference clock. The lock detector generates a mismatch signal based on a comparison between the phases of the reference clock and the output clock to generate a compare result. The lock detector delays the compare result by a time period Td and AND the delayed compare result with the compare result to generate the mismatch signal. The lock detector includes a lock-counter that counts a number of reference clock cycles when the mismatch signal remains at 0. The lock signal indicates that a lock-state is achieved when the number of counted reference clock cycles equals a set-value.

Abstract: This application discloses a device that has a power-on reset generator. The power-on reset generator can include a power-on detector that receives an input electrical signal and outputs a digital signal that has predetermined value when the voltage of the input electrical signal exceeds a threshold voltage. The power-on detector can include multiple voltage-shaping elements arranged in series. Each voltage-shaping element can have a P-channel transistor and an N-channel transistor that differs in strength with respect to the P-channel transistor. The power-on detector can also include a switch that locks the digital signal at the predetermined value when the voltage of the input electrical signal exceeds the voltage threshold. In addition to the power-on detector, the power-on reset generator can include a digital delay that receives both the digital signal and a clock signal.

Abstract: A speed monitor circuit integrated in an integrated circuit (IC) determines the speed of the IC. The speed monitor circuit includes an oscillator that generates an oscillator signal. A speed determining circuit generates a first count based on transitions of the oscillator signal. A match signal corresponds to the speed of the oscillator based on the first count and a reference count.

Abstract: Aspects of the disclosure provide a circuit using digital techniques to generate a differential signal with a low skew. The circuit can include a first switching element configured to receive at least a first logic value and a second logic value, and output a first signal of the differential signal, the second logic value being different from the first logic value. Further, the circuit can include a second switching element configured to receive at least the first logic value and the second logic value, and output a second signal of the differential signal.

Abstract: An integrated circuit comprises an oscillator that generates an oscillator signal. A first counter generates a first count based on transitions of the oscillator signal. A first circuit generates a match signal based on the first count and a reference count. A second counter generates a second count that is initialized at a starting count and adjusts the second count based on transitions of a reference clock signal. An output circuit outputs an oscillator speed based on the second count and the match signal. The oscillator speed is defined by a range that is independent of a frequency of the reference clock signal.

Abstract: Aspects of the disclosure provide a fine tunable digital delay circuit that can be applied in a high frequency digital circuit. Further, the digital delay circuit can utilize a level restoring technique to enable a wide tunable delay range. The delay circuit can include a delay element configured to receive an input signal at an input node and output a controlled signal having a controlled rise time and a controlled fall time at a controlled node, a first plurality of transistors configured to bias a supply node of the delay element to govern the controlled rise time of the controlled signal, and a second plurality of transistors configured to bias a ground node of the delay element to govern the controlled fall time of the controlled signal. The delay circuit can further include a restoring circuit configured to charge or discharge the controlled node.

Abstract: Aspects of the disclosure provide a circuit using digital techniques to generate a differential signal with a low skew. The circuit can include a first switching element configured to receive at least a first logic value and a second logic value, and output a first signal of the differential signal, the second logic value being different from the first logic value. Further, the circuit can include a second switching element configured to receive at least the first logic value and the second logic value, and output a second signal of the differential signal.

Abstract: A circuit and related method of monitoring performance of an integrated circuit is provided comprising: using a variable oscillator that has an oscillation time period that varies within an expected range with variations in one or more of process, voltage or temperature to provide a signal that causes a count of a first counter to change at rate proportional to an oscillation frequency of the variable oscillator; using a clock source that has a frequency that substantially does not vary with variations in one or more of process, time or voltage to cause a count of a second counter to change at rate proportional to an oscillation frequency of the clock source; setting the second counter to start a count from a start; determining when the first counter has counted a reference count; and providing as a circuit speed, a value indicative of a count value produced by the second counter at about the moment when first counter finishes counting the count interval.