Abstract: A device having a plurality of thin film photovoltaic cells (PV) formed over a passivation layer. The device comprises a plurality of thin film photovoltaic (PV) cells formed over the passivation layer, each PV cell includes at least a lower conducting layer (LCL) and an upper conducting layer (UCL); and a conducting path connecting at least a UCL of a first PV cell to at least a LCL of a second PV cell, wherein at least a first array of PV cells comprised of at least a first portion of the plurality of PV cells is connected by the respective UCL and LCL of each PV cell to provide a first voltage output. In an embodiment the passivation layer is formed over a target integrated circuit (TIC), the TIC having a top surface and a bottom surface.

Abstract: A system for energy harvesting comprises a first interface for receiving energy from at least one renewable energy source (ERS); a second interface coupled to at least one load circuit; a third interface coupled to an least one primary energy storage (PES); a DC-to-DC converter connected to one of a single inductor and a single capacitor; a switching circuitry connected to the first, second, and third interfaces and the DC-to-DC converter; a control unit connected to the DC-to-DC converter and the switching circuitry, the control unit controls the system to operate in an operation mode including any one of: provide energy from the ERS to the at least one load via the DC-to-DC converter, charge the least one PES from the at least one ERS via the DC-to-DC converter, and provide energy from the at least one PES to the at least one load circuit via the DC-to-DC converter.

Abstract: A device having a plurality of thin film photovoltaic cells (PV) formed over a passivation layer. The device comprises a plurality of thin film photovoltaic (PV) cells formed over the passivation layer, each PV cell includes at least a lower conducting layer (LCL) and an upper conducting layer (UCL); and a conducting path connecting at least a UCL of a first PV cell to at least a LCL of a second PV cell, wherein at least a first array of PV cells comprised of at least a first portion of the plurality of PV cells is connected by the respective UCL and LCL of each PV cell to provide a first voltage output. In an embodiment the passivation layer is formed over a target integrated circuit (TIC), the TIC having a top surface and a bottom surface.

Abstract: A target integrated circuit (TIC) having a top conductive layer (TCL) that may be connected to a plurality of cells that are further integrated over the TIC. Each of the plurality of cells comprises two conductive layers, a lower conductive layer (LCL) below the cell and an upper conductive layer (UCL) above the cell. Both conductive layers may connect to the TCL of the TIC to form a super IC structure combined of the TIC and the plurality of cells connected thereto. Accordingly, conductivity between the TIC as well as auxiliary circuitry to the TIC maybe achieved.

Abstract: An integrated circuit (IC) combination of a target integrated circuit (TIC) and a plurality of thin film photovoltaic cells (PV) connected thereto. The IC comprises a target integrated circuit (TIC) having a top surface and a bottom surface; a plurality of thin film photovoltaic (PV) cells formed over at least one of the top surface and the bottom surface of the TIC, each PV cell includes at least a lower conducting layer (LCL) and an upper conducting layer (UCL); and a conducting path connecting at least a UCL of a first PV cell to at least a LCL of a second PV cell, wherein at least a first array of PV cells comprised of at least a first portion of the plurality of PV cells is connected by the respective UCL and LCL of each PV cell to provide a first voltage output.

Abstract: A system for energy harvesting comprises a first interface for receiving energy from at least one renewable energy source (ERS); a second interface coupled to at least one load circuit; a third interface coupled to an least one primary energy storage (PES); a DC-to-DC converter connected to one of a single inductor and a single capacitor; a switching circuitry connected to the first, second, and third interfaces and the DC-to-DC converter; a control unit connected to the DC-to-DC converter and the switching circuitry, the control unit controls the system to operate in an operation mode including any one of: provide energy from the ERS to the at least one load via the DC-to-DC converter, charge the least one PES from the at least one ERS via the DC-to-DC converter, and provide energy from the at least one PES to the at least one load circuit via the DC-to-DC converter.

Abstract: An integrated circuit (IC) combination of a target integrated circuit (TIC) and a plurality of thin film photovoltaic cells (PV) connected thereto. The IC comprises a target integrated circuit (TIC) having a top surface and a bottom surface; a plurality of thin film photovoltaic (PV) cells formed over at least one of the top surface and the bottom surface of the TIC, each PV cell includes at least a lower conducting layer (LCL) and an upper conducting layer (UCL); and a conducting path connecting at least a UCL of a first PV cell to at least a LCL of a second PV cell, wherein at least a first array of PV cells comprised of at least a first portion of the plurality of PV cells is connected by the respective UCL and LCL of each PV cell to provide a first voltage output.

Abstract: A target integrated circuit (TIC) having a top conductive layer (TCL) that may be connected to a plurality of cells that are further integrated over the TIC. Each of the plurality of cells comprises two conductive layers, a lower conductive layer (LCL) below the cell and an upper conductive layer (UCL) above the cell. Both conductive layers may connect to the TCL of the TIC to form a super IC structure combined of the TIC and the plurality of cells connected thereto. Accordingly, conductivity between the TIC as well as auxiliary circuitry to the TIC maybe achieved.

Abstract: A controlled-slope output buffer is furnished to reduce electro-magnetic interference (EMI) and ground bounce noise which commonly arises in output buffers in a VLSI chip. In the controlled-slope buffer, output current pulses are shaped to reduce higher frequency signal components. Corrective shaping of the electrical signals by the controlled-slope buffer is effective in reducing EMI emissions in a frequency range from 200 to 1000 MHz. Output signals of the controlled-slope output buffer have voltage slopes which are substantially the same as output signals generated by conventional output buffers. However, the controlled-slope output buffer generates output signals in which the shape of the current pulse is greatly improved for reducing EMI and ground bounce noise. In the controlled-slope buffers according to the present invention, current pulses have a triangular shape when they are drawn in the time domain.

Abstract: An accurate peak-to-peak detector, readily implemented in CMOS and consuming low power. The peak-to-peak detector includes a clamp portion (circuit) followed by a peak-detect portion (circuit), each of which circuits includes at least one active component (e.g., transistor). The clamp circuit receives an input signal having an alternating current (AC) component via an input coupling capacitor which outputs a voltage on a line to the peak-detect circuit. The clamp circuit includes either a passive load element (e.g., a resistor), or an active load element (e.g., a CMOS transistor), so that the clamp circuit bleeds current from the input coupling capacitor, and any slow drift in the DC level of the input voltage will be followed. The peak-detect circuit follows the voltage output by the coupling capacitor, and includes either a passive load element (e.g., a resistor) or an active load element (e.g.

Abstract: An active filter includes a capacitor and a resistor coupled in parallel to an input terminal; a first current conveyor coupled between the capacitor and an output terminal; a second current conveyor coupled between the resistor and the output terminal; and a second capacitor coupled between the output terminal and ground. Proportionality constants between input and output currents of the current conveyors can be adjusted to reduce capacitance in the active filter and reduce the area required to fabricate the active filter in an integrated circuit. The active filter can replace a conventional loop filter in a phase-locked loop of a data separator integrated circuit. In a phase-locked loop, the polarity of a charge pump can be reversed to compensate for current reversal by the current conveyors in the active filter.

Abstract: A power efficient class A-B amplifier provides 20 dB amplification for a low capacitive load such as a 40 to 80 MHz clock signal in a crystal oscillator circuit. The amplifier includes two bias-and-clamp circuits coupled between an input stage and the gates of an N-channel transistor and a P-channel transistor. The N-channel and P-channel transistors are connected in series between VCC and ground and form an output stage. The bias-and-clamp circuits bias the N-channel and P-channel transistors in weak inversion for maximum amplification and clamp an input voltage to increase noise immunity and reduce power use. In one embodiment, each bias-and-clamp circuit includes two pairs of series connected transistors. A first pair is connected in series with a constant current source and form current mirrors with a second pair of transistors. A node between transistors in the second pair is connected to the gate of a transistor in the output stage and to the input voltage.