Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.

Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.

Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.

Abstract: An electrolytic capacitor includes a metal case, a porous pellet anode disposed within the metal case, an electrolyte disposed within the metal case, and a cathode element formed of an electrophoretically deposited metal or metal oxide powder of a uniform thickness disposed within the metal case and surrounding the anode. A method of manufacturing an electrolytic capacitor includes providing a metal case, electrophoretically depositing on the metal can a refractory metal oxide to form a cathode element, and placing a porous pellet anode and an electrolyte within the can such that the cathode element and the anode element being separated by the electrolyte.

Abstract: A bulk capacitor includes a first electrode formed of a metal foil and a semi-conductive porous ceramic body formed on the metal foil. A dielectric layer is formed on the porous ceramic body for example by oxidation. A conductive medium is deposited on the porous ceramic body filling the pores of the porous ceramic body and forming a second electrode. The capacitor can then be encapsulated with various layers and can include conventional electrical terminations. A method of manufacturing a bulk capacitor includes forming a conductive porous ceramic body on a first electrode formed of a metal foil, oxidizing to form a dielectric layer and filling the porous body with a conductive medium to form a second electrode. A thin semi-conductive ceramic layer can also be disposed between the metal foil and the porous ceramic body.

Abstract: A bulk capacitor includes a first electrode formed of a metal foil and a semi-conductive porous ceramic body formed on the metal foil. A dielectric layer is formed on the porous ceramic body for example by oxidation. A conductive medium is deposited on the porous ceramic body filling the pores of the porous ceramic body and forming a second electrode. The capacitor can then be encapsulated with various layers and can include conventional electrical terminations. A method of manufacturing a bulk capacitor includes forming a conductive porous ceramic body on a first electrode formed of a metal foil, oxidizing to form a dielectric layer and filling the porous body with a conductive medium to form a second electrode. A thin semi-conductive ceramic layer can also be disposed between the metal foil and the porous ceramic body.

Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.

Abstract: A dielectric ceramic composition has a dielectric constant, K, of at least 200 and a dielectric loss, DF, of 0.0006 or less at 1 MHz. The dielectric ceramic composition may be formed by sintering by firing in air without a controlled atmosphere. The dielectric ceramic composition may have a major component of 92.49 to 97.5 wt. % containing 60.15 to 68.2 wt. % strontium titanate, 11.02 to 23.59 wt. % calcium titanate and 7.11 to 21.32 wt. % barium titanate; and a minor component of 2.50 to 7.51 wt. % containing 1.18 to 3.55 wt. % calcium zirconate, 0.50 to 1.54 wt. % bismuth trioxide, 0.2 to 0.59 wt. % zirconia, 0.02 to 0.07 wt. % manganese dioxide, 0.12 to 0.35 wt. % zinc oxide, 0.12 to 0.35 wt. % lead-free glass frit, 0.24 to 0.71 wt. % kaolin clay and 0.12 to 0.35 wt. % cerium oxide. UHF antennas and monolithic ceramic components may use the dielectric ceramic composition.

Abstract: A bulk capacitor includes a first electrode formed of a metal foil and a semi-conductive porous ceramic body formed on the metal foil. A dielectric layer is formed on the porous ceramic body for example by oxidation. A conductive medium is deposited on the porous ceramic body filling the pores of the porous ceramic body and forming a second electrode. The capacitor can then be encapsulated with various layers and can include conventional electrical terminations. A method of manufacturing a bulk capacitor includes forming a conductive porous ceramic body on a first electrode formed of a metal foil, oxidizing to form a dielectric layer and filling the porous body with a conductive medium to form a second electrode. A thin semi-conductive ceramic layer can also be disposed between the metal foil and the porous ceramic body.

Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

Abstract: An electrolytic capacitor includes a metal case, a porous pellet anode disposed within the metal case, an electrolyte disposed within the metal case, and a cathode element formed of an electrophoretically deposited metal or metal oxide powder of a uniform thickness disposed within the metal case and surrounding the anode. A method of manufacturing an electrolytic capacitor includes providing a metal case, electrophoretically depositing on the metal can a refractory metal oxide to form a cathode element, and placing a porous pellet anode and an electrolyte within the can such that the cathode element and the anode element being separated by the electrolyte.

Abstract: A dielectric ceramic composition has a dielectric constant, K, of at least 200 and a dielectric loss, DF, of 0.0006 or less at 1 MHz. The dielectric ceramic composition may be formed by sintering by firing in air without a controlled atmosphere. The dielectric ceramic composition may have a major component of 92.49 to 97.5 wt. % containing 60.15 to 68.2 wt. % strontium titanate, 11.02 to 23.59 wt. % calcium titanate and 7.11 to 21.32 wt. % barium titanate; and a minor component of 2.50 to 7.51 wt. % containing 1.18 to 3.55 wt. % calcium zirconate, 0.50 to 1.54 wt. % bismuth trioxide, 0.2 to 0.59 wt. % zirconia, 0.02 to 0.07 wt. % manganese dioxide, 0.12 to 0.35 wt. % zinc oxide, 0.12 to 0.35 wt. % lead-free glass frit, 0.24 to 0.71 wt. % kaolin clay and 0.12 to 0.35 wt. % cerium oxide. UHF antennas and monolithic ceramic components may use the dielectric ceramic composition.

Abstract: An electronic component such as a capacitor includes a substrate having first and second principal surfaces, a dielectric layer overlaying the first principal surface of the substrate, a first electrode, and a second electrode. There is a passivation layer overlaying the first and second electrodes, a first opening being formed in the passivation layer over the first electrode and a second opening being formed in the passivation layer over the second electrode. A first bottom electrode termination is positioned in the first opening and a second bottom electrode termination is positioned in the second opening. The first bottom electrode termination is electrically connected to the first electrode and the second bottom electrode termination is electrically connected to the second electrode. A standoff is positioned between the first bottom electrode termination and the second bottom electrode termination and attached to the passivation layer to thereby provide support for the electronic component when mounted.

Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

Abstract: An electronic component such as a capacitor includes a substrate having first and second principal surfaces, a dielectric layer overlaying the first principal surface of the substrate, a first electrode, and a second electrode. There is a passivation layer overlaying the first and second electrodes, a first opening being formed in the passivation layer over the first electrode and a second opening being formed in the passivation layer over the second electrode. A first bottom electrode termination is positioned in the first opening and a second bottom electrode termination is positioned in the second opening. The first bottom electrode termination is electrically connected to the first electrode and the second bottom electrode termination is electrically connected to the second electrode. A standoff is positioned between the first bottom electrode termination and the second bottom electrode termination and attached to the passivation layer to thereby provide support for the electronic component when mounted.

Abstract: A surface mount chip capacitor includes a metal substrate, a conductive powder element including a valve metal and partially surrounding the metal substrate with the metal substrate extending outwardly from the conductive powder towards the anode end of the surface mount chip capacitor, a silver body cathode at least partially surrounding the conductive powder element, a coating formed by vapor-phase deposition surrounding the silver body cathode, an insulative material formed about a portion of the substrate extending outwardly from the conductive powder, a conductive coating formed around the metal substrate at the anode end of the surface mount chip capacitor, an end termination anode electrically connected to the conductive coating at the anode end of the surface mount chip capacitor, and an end termination cathode electrically connected to the silver body cathode at the cathode end of the surface mount chip capacitor.

Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

Abstract: A surface mount chip capacitor includes a metal substrate, a conductive powder element comprising a valve metal and partially surrounding the metal substrate with the metal substrate extending outwardly from the conductive powder towards the anode end of the surface mount chip capacitor, a silver body cathode at least partially surrounding the conductive powder element, a coating formed by vapor-phase deposition surrounding the silver body cathode, an insulative material formed about a portion of the substrate extending outwardly from the conductive powder, a conductive coating formed around the metal substrate at the anode end of the surface mount chip capacitor, an end termination anode electrically connected to the conductive coating at the anode end of the surface mount chip capacitor, and an end termination cathode electrically connected to the silver body cathode at the cathode end of the surface mount chip capacitor.

Abstract: A crystalline substrate based device including a crystalline substrate having formed thereon a microstructure and at least one packaging layer which is formed over the microstructure and defines therewith at least one gap between the crystalline substrate and the at least one packaging layer and at least one opening in the packaging layer communicating with the at least one gap.

Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.