Patents by Inventor Revanasiddaiah Prabhuswamy Mathada

Revanasiddaiah Prabhuswamy Mathada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10922013
    Abstract: The disclosure relates in some aspects to suspending a read for a non-volatile memory (NVM) device. For example, a lower priority read may be suspended to enable a higher priority read to occur. Once the higher priority read completes, the lower priority read is resumed. To improve the efficiency of the read suspension, the lower priority read may be suspended once data sensing at a current level of the NVM device completes. The data for each level that has already been sensed is then stored so that this data does not need to be sensed again. Once the lower priority read is resumed, the data sensing starts at the next level of the NVM device. The data output for the lower priority read thus includes the stored data for any levels read before the read is suspended, along with the data from the levels read after the read is resumed.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: February 16, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Revanasiddaiah Prabhuswamy Mathada, Saugata Das Purkayastha, Anantharaj Thalaimalaivanaraj, Nisha Padattil Kuliyampattil
  • Patent number: 10915475
    Abstract: Aspects of the disclosure provide for management of a flash translation layer (FTL) for a non-volatile memory (NVM) in a Solid State Drive (SSD). The methods and apparatus provide a logical to physical (L2P) table where a first portion of the table is used for mapping frequently accessed hot data to a first subdrive in the NVM. Additionally, a second portion of the L2P table is provided for mapping cold data less frequently accessed than the hot data to a second subdrive, where logical blocks for storing the cold data in the second subdrive are larger than logical blocks storing the hot data in the first subdrive. Separation of the L2P table into hot and cold subdrives reduces the L2P table size that is needed in RAM for logical to physical memory mapping, while at the same time provides lower write amplification and latencies, especially for large capacity SSDs.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: February 9, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Rishabh Dubey, Saugata Das Purkayastha, Chaitanya Kavirayani, Sampath Raja Murthy, Nitin Gupta, Revanasiddaiah Prabhuswamy Mathada
  • Publication number: 20190310795
    Abstract: The disclosure relates in some aspects to suspending a read for a non-volatile memory (NVM) device. For example, a lower priority read may be suspended to enable a higher priority read to occur. Once the higher priority read completes, the lower priority read is resumed. To improve the efficiency of the read suspension, the lower priority read may be suspended once data sensing at a current level of the NVM device completes. The data for each level that has already been sensed is then stored so that this data does not need to be sensed again. Once the lower priority read is resumed, the data sensing starts at the next level of the NVM device. The data output for the lower priority read thus includes the stored data for any levels read before the read is suspended, along with the data from the levels read after the read is resumed.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 10, 2019
    Inventors: Revanasiddaiah Prabhuswamy Mathada, Saugata Das Purkayastha, Anantharaj Thalaimalaivanaraj, Nisha Padattil Kuliyampattil
  • Patent number: 10394706
    Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to receive a plurality of non-sequential memory access commands directed to the set of non-volatile memory cells, predict a predicted memory access command based on the plurality of non-sequential memory access commands, and access the set of non-volatile memory cells according to the predicted memory access command.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: August 27, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Saugata Das Purkayastha, Revanasiddaiah Prabhuswamy Mathada
  • Publication number: 20190129834
    Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to receive a plurality of non-sequential memory access commands directed to the set of non-volatile memory cells, predict a predicted memory access command based on the plurality of non-sequential memory access commands, and access the set of non-volatile memory cells according to the predicted memory access command.
    Type: Application
    Filed: November 2, 2017
    Publication date: May 2, 2019
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Saugata Das Purkayastha, Revanasiddaiah Prabhuswamy Mathada
  • Publication number: 20190114272
    Abstract: Aspects of the disclosure provide for management of a flash translation layer (FTL) for a non-volatile memory (NVM) in a Solid State Drive (SSD). The methods and apparatus provide a logical to physical (L2P) table where a first portion of the table is used for mapping frequently accessed hot data to a first subdrive in the NVM. Additionally, a second portion of the L2P table is provided for mapping cold data less frequently accessed than the hot data to a second subdrive, where logical blocks for storing the cold data in the second subdrive are larger than logical blocks storing the hot data in the first subdrive. Separation of the L2P table into hot and cold subdrives reduces the L2P table size that is needed in RAM for logical to physical memory mapping, while at the same time provides lower write amplification and latencies, especially for large capacity SSDs.
    Type: Application
    Filed: October 12, 2017
    Publication date: April 18, 2019
    Inventors: Rishabh Dubey, Saugata Das Purkayastha, Chaitanya Kavirayani, Sampath Raja Murthy, Nitin Gupta, Revanasiddaiah Prabhuswamy Mathada