Abstract: A feedback system such as a phase locked loop (PLL) includes a second feedback loop which responds when a VCO control voltage is near either end of its range, by slowly adjusting additional tuning elements which control the VCO frequency. The second feedback loop is arranged to cause a slow enough change in the VCO frequency that the first traditional feedback loop adjusts the control voltage quickly enough in a direction toward its mid-range value to keep the VCO frequency substantially unchanged. The second feedback loop advantageously incorporates one or more digital control signals which preferably change no more than one bit at a time and with a controlled slow ramp rate. As a result, the PLL maintains phase accuracy so that the operation of the PLL, including subtle specifications such as input data jitter tolerance or output jitter generation when used for clock and data recovery applications, is not negatively impacted.

Abstract: A technique for expanding an input signal includes receiving the input signal at a first node of a voltage expander and generating a plurality of expanded signals on different outputs of the voltage expander responsive to the input signal. In certain embodiments, each of the expanded signals has a different magnitude at a respective fixed offset from the input signal.

Abstract: An optical disk pickup system includes an array of photodiodes 101 for converting photons reflected from an optical disk into a plurality of electrical signals each representing a channel. Driving circuitry 407, 408 drives at least one of the electrical signals as a current across a conductor of a flexible cable 403. A low impedance load 404 converts the electrical signal driven across the conductor as a current into a voltage for further processing.

Abstract: An optical disk pickup system includes an array of photodiodes 101 for converting photons reflected from an optical disk into a plurality of electrical signals each representing a channel. Driving circuitry 407, 408 drives at least one of the electrical signals as a current across a conductor of a flexible cable 403. A low impedance load 404 converts the electrical signal driven across the conductor as a current into a voltage for further processing.

Abstract: An optical disk pickup system includes an array of photodiodes 101 for converting photons reflected from an optical disk into a plurality of electrical signals each representing a channel. Driving circuitry 407, 408 drives at least one of the electrical signals as a current across a conductor of a flexible cable 403. A low impedance load 404 converts the electrical signal driven across the conductor as a current into a voltage for further processing.

Abstract: A system and method is disclosed for calibrating comparators of an ADC while the ADC continues to operate in an uninterrupted fashion. Groups (banks) of interleaved comparators may be calibrated at random or psuedo-random times while the ADC is performing conversions without the addition of extra “proxy” or replacement comparators. More particularly, at periodic intervals the comparators of one bank may be disconnected from the standard ADC circuitry for calibration or auto-zeroing while the comparators in the remaining bank(s) are left in the data conversion path. In order to prevent a significant degradation in the conversion quality, logic downstream of the comparators provides the necessary adjustments to accommodate for the removal of the comparators and outputs a word of the desired bit length. The multi-bank ADC is particularly advantageous for use with optical data storage systems.

Abstract: An optical disk pickup system 400 using current mode signal transmission is disclosed. An operational amplifier 404 has an input for receiving an electrical signal and a feedback loop including a current path of a first transistor 405 of a first size, transistor 405 having a control terminal at a preselected voltage. A conductor 402 is coupled to an output of operational amplifier 404 for transmitting the electrical signal as a current. A second transistor 406 of a second size has a current path in series with a conductor 402 and a control terminal coupled to the preselected voltage, transistors 405, 406 forming a current divider.

Abstract: Analog modulator circuitry 401 includes an integrator 707. First switched capacitor circuitry 710, 711, 713, 714 selectively samples a first amount of charge from a feedback signal and couples that first amount of charge to the first and second inputs of the integrator. Second switched capacitor circuitry 711, 714, 716, 717 selectively samples a second amount of charge from the feedback signal and couples that second amount of charge to the first and second inputs of the integrator stage to selectively compensate for an offset of an input signal to the integrator with respect to a reference voltage.