Patents by Inventor Rex Hsueh

Rex Hsueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8271737
    Abstract: A device, system and method in which data in a write cache, that must at some point be written to non-volatile memory, is written to non-volatile memory after expiration of a threshold time period during which no new host commands are received. If either the last dirty entry is written back or a host command is received during the write-back process, the time threshold time period and auto-flush process is restarted.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: September 18, 2012
    Assignee: Spansion LLC
    Inventors: Richard Chen, Rex Hsueh, Ping Hou
  • Publication number: 20100306448
    Abstract: A device, system and method in which data in a write cache, that must at some point be written to non-volatile memory, is written to non-volatile memory after expiration of a threshold time period during which no new host commands are received. If either the last dirty entry is written back or a host command is received during the write-back process, the time threshold time period and auto-flush process is restarted.
    Type: Application
    Filed: May 27, 2009
    Publication date: December 2, 2010
    Inventors: Richard Chen, Rex Hsueh, Ping Hou
  • Patent number: 7440392
    Abstract: A deinterleaver module in an OFDM wireless transceiver includes partitioned memory banks for storage of code word fragments from an interleaved data stream, each code word fragment associated with a prescribed subcarrier frequency. Each code word fragment includes a prescribed number of code word bits based on a prescribed modulation of the interleaved data stream, and the code word bits for each code word fragment are written into respective selected locations of the corresponding memory bank based on the prescribed modulation and the corresponding prescribed subcarrier frequency. The deinterleaver module outputs deinterleaved data from the memory banks based on parallel output of the respective stored code word bits from a selected address of the memory banks.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: October 21, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Chien-Meen Hwang, Peter Chan, Howard Hicks, Chih (Rex) Hsueh, Liping Zhang
  • Patent number: 7292527
    Abstract: An OFDM receiver configured for measuring frequency error based on comparing prescribed pilot tones from a prescribed group of consecutive symbols in a received OFDM signal. A complex conjugate generator is configured for generating complex conjugates of the prescribed pilot tones of a first subgroup of the consecutive symbols. A multiplier is configured for generating a complex pilot product, for each symbol subgroup position, by multiplying the pilot tones of a second subgroup symbol at the corresponding symbol subgroup position with the respective complex conjugates of the first subgroup symbol at the corresponding symbol subgroup position. A complex summation circuit sums the complex pilot products of the symbol subgroup positions to obtain an accumulated complex value. A error calculator calculates the frequency error from the accumulated complex value for use in correcting frequency offset.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: November 6, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Xu Zhou, Chihming (Norman) Chen, Chih (Rex) Hsueh, Orlando Canelones
  • Patent number: 7233612
    Abstract: A deinterleaver module in an OFDM wireless transceiver includes partitioned memory banks for storage of code word fragments from an interleaved data stream, each code word fragment associated with a prescribed subcarrier frequency. Each code word fragment includes a prescribed number of code word bits based on a prescribed modulation of the interleaved data stream, and the code word bits for each code word fragment are written into respective selected locations of the corresponding memory bank based on the prescribed modulation and the corresponding prescribed subcarrier frequency. Write enable signals, bit selection signals, and address signals for each of the code word bits are generated based on applying logical operands to a cascaded sequence of successively delayed signals synchronous with a local clock signal. The deinterleaver module outputs deinterleaved data from the memory banks based on parallel output of the respective stored code word bits from a selected address of the memory banks.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: June 19, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Liping Zhang, Peter Chan, Howard Hicks, Chih (Rex) Hsueh, Chien-Meen Hwang