Abstract: The present invention relates to a system and method (“Bid System”) for topologically subdividing and defining the detail scope of work and for inter-linking construction plans and specifications to construction contracts and subcontracts. The Bid System permits full, clear and unambiguous definition of the scope of work under each subcontract, so as to eliminates errors and uncertainty relating to contract performance. The Bid System establishes a series of electronic overlays to the digitized construction plans corresponding to different trades or categories of work, in which each overlay may be divided into a series of optimized topological subdivisions or “boxes” which uniquely identify and locate on the plans a portion of the work to be performed. The system includes linkage of the overlays and boxes to the subcontracts whereby the scope of work to be bid is accurately associated or “mapped” to corresponding regions and overlay category on the architectural drawings or construction plans.

Abstract: An image processing system (10) includes an array (12) of detectors (14), each of which is designed to produce a current proportional to incident radiation. This system provides image processing at a viable sampling rate even for very large arrays and permits very efficient determination of single element detections. The modulation functions are supplied from a weighted summer (18). The weighted summer applies an invertible matrix of weights to a series of orthogonal Walsh functions defined over a predetermined sampling interval, the Walsh functions being generated by a function generator (16). The modulated outputs of the array are combined by summer 20 and distributed among parallel channels by a divider (22). Correlators (24) correlate the signal in each channel with a respective of the original Walsh functions. The correlated outputs are digitized by analog-to-digital converters for transmission and processing by a digital processor (28).

Abstract: A method for transferring data through a network of intelligent control stations (S1-S14) uses decentralized control techniques and associates the intelligent stations (S1-S14) with an addressing scheme which defines a hypercube.

Abstract: A real-time image processing system (800) includes an array (810) of storage elements (813), each of which is designed to store a signal representative of radiation of interest. This system (800) provides image processing at a viable sampling rate even for very large arrays and permits very efficient determination of single element detections.Time-varying orthogonal functions are created by digital processor (804). The processor (804) modulates these base time-varying orthogonal functions by applying to them a matrix of weighing functions. These modulated time-varying orthogonal functions are then applied to selected storage elements (813).The modulated outputs of the array (810) are combined (838) and distributed among parallel channels (886, 888, 890). Demodulators correlate the signal in each channel with a respective of the original orthogonal functions. The demodulated outputs are digitized by an analog-to digital converter (908) for processing by a digital processor (908).

Abstract: An image processing system (10) includes a focal plane array (652) of image detectors (654), each of which produces a signal proportional to incident radiation. The image data signals are arranged in groups, such as rows or columns that are respectively associated with a plurality of select circuits (656) which sequentially select the signals for correction by an associated offset and gain correction circuit (658). The correction circuit includes a pair of shift registers (672, 694) for respectively storing data related to a desired gain correction and offset correction of the data image signal. Under control of a processor, the stored correction data is used to pass the image data signal through a selectively configured network of resistive elements (720, 722) to thereby correct the gain and offset of the signal.

Abstract: An image processing system (10, 800, 804) includes an array (12, 652) of detectors (14, 654), each of which produces a signal proportional to incident radiation. The image data produced in the array (12, 652) is transferred to a "pseudo" array (662) of data storage elements (664) for temporary storage therein. A preprocessing circuit (812) includes a modulator (837) associated with each pixel location for modulating pixel data obtained from the pseudo array, and one or more demodulators (835) for demodulating the combined modulated data. The preprocessor generates pointers for use by a processor (804) in quickly identifying areas of interesting pixels.

Abstract: An image processing system 10 includes an array (12) of detectors 14, each of which is designed to produce a current proportional to incident radiation. This system provides image processing at a viable sampling rate even for very large arrays and permits very efficient determination of single element detections.The modulation functions supplied from a weighted summer (18). The weighted summer applies an invertible matrix of weights to a series of orthonormal Walsh functions defined over a predetermined sampling interval, the Walsh functions being generated by a function generator (16).The modulated outputs of the array are combined by a summer (20) and distributed among parallel channels by a divider (22). Correlators (24) correlate the signal in each channel with a respective one of the original Walsh functions. The correlated outputs are digitized by analog-to-digital converters for transmission and processing by a digital processor (28).

Abstract: A time base converter employs a two position, phase lock loop (40) to write twice orthogonally spaced signals into a split phase memory (34), which in turn can be read out at the timing rate of an incorporating communications system. The converter effectively converts the time base of signals read out of a demodulator (14) to the system time base, thus permitting use of the demodulator in computer based, digital processing systems. Readout of the signals is facilitated by a pair of marker tones f.sub.H, f.sub.L which are introduced into the signal on the upper and lower sides of the input bandwidth. The signal is digitized by A/D converters (28, 30) and the resulting data is employed to drive the phase lock loop. The phase lock loop includes a counter (44) driven by a voltage controlled oscillator (46) which time shares a pair of loop filters (52, 54) that respectively pass the marker tones f.sub.H, f.sub.L.

Abstract: A multi-arm frequency sweep generator 10 provides frequency sweep characterized by precise waveform control (linearization), steep slopes, and a high repetition rate. An impulser (12) generates pulses which are distributed by a multiplexer (14) to the multi-arms of the frequency sweep generator. Each arm includes a reflective array compressor (RAC) 16 for dispersion a throughgoing pulse into a frequency sweep of low enough slope that it can be effective corrected by means of complex multiplying digital-to-analog converters (18). The corrected sweeps are summed by a demultiplexer (20). A compressor RAC (22) compresses the summed output to provide sweeps with slopes steeper than would normally be correctable by the MDACs.

Abstract: A device for transforming N-Frequency Division Multiplexed (FDM) channels (21) of modulated signals into individually accessible streams (46) of demodulated data employs a Fourier transform processor (10) to transform the N-FDM channels into a single, TDM (Time Division Multiplex) channel of data, a single demodulator (12) for demodulating the single TDM channel and a demultiplexer (14) for demultiplexing the single channel of TDM data. The symbol segments of the N-FDM channels are synchronized with each other using an error signal generator (78) and a dither technique in which a symbol window is shifted back and forth to determine whether the symbol segments are early, on time or late. In a preferred form, the demodulator and error signal generator are implemented using digital techniques.

Abstract: An analog surface acoustic wave demodulator includes a calibration section (10) for compensating for distortions, a calibrated frequency sweep (20), a pair of dispersion sections formed by reflective array compressors (24, 26 and 36, 38), a synchronizer (18, 22, 28, 118), a timing signal generator (42) and a temperature compensating readout circuit (40). Frequency domain compensations introduced at the signal input by the calibration section and by the frequency sweep compensate for distortions in time domain at the output of the demodulator. The calibration function applied to the input signal and to the sweep is stored in ROM's (14, 44) in the form of complex digital words. Timing and address generators (12, 42) read the words from the Rom's to complex multipliers (16, 52) such that each symbol period is multiplied by the sequence of words. Each complex digital word corresponds to an amplitude and phase modulation on the incoming signal over a fraction of a symbol period.

Abstract: A system for generating a sequence of pulses of carrier having individually selectable frequencies employs a pulsed oscillator for providing a single pulse of a carrier signal having a predetermined frequency. The single pulse is applied to a dispersive filter imparting a delay to signals dependent of their spectral content. The relatively broad spectrum of the single pulse is converted by the dispersive filter into a swept frequency pulse of much longer duration than the input pulse to the filter. The expanded signal is mixed with a set of mixing frequencies to provide a set of expanded signals, each of which is then gated to attain spectral portions having desired average values of frequency. The expanded signals are then summed together and applied to a compressive filter which operates in the mirror-image format to the dispersive filter.

Abstract: A time base converter employs a two position, phase lock loop (40) to write twice orthogonally spaced signals into a split phase memory (34), which in turn can be read out at the timing rate of an incorporating communications system. The converter effectively converts the time base of signals read out of a demodulator (14) to the system time base, thus permitting use of the demodulator in computer based, digital processing systems. Readout of the signals is facilitated by a pair of marker tones f.sub.H, f.sub.L which are introduced into the signal on the upper and lower sides of the input bandwidth. The signal is digitized by A/D converters (28, 30) and the resulting data is employed to drive the phase lock loop. The phase lock loop includes a counter (44) driven by a voltage controlled oscillator (46) which time shares a pair of loop filters (52, 54) that respectively pass the marker tones f.sub.H, f.sub.L.

Abstract: A signal processor (11), such as a spectrum analyzer or SAW demodulator, defines a signal stream from a frequency division multiplexed (FDM) input (13) to a time division multiplexed (TDM) output (41). The signal stream includes a bivariate processor (23) for applying a function to the through-going signal.The function is produced by a function generator (37) in response to a trigger (33) located remotely from the signal stream. To ensure timely convergence of signal and function, a phase-locked loop based on on/off modulated marker tones f.sub.H and f.sub.L is provided. The phase-locked loop includes an amplitude detector (27) for detecting the amplitudes of marker pulses which are transformed marker tone segments. The amplitudes are compared by a comparator (29) to form a discriminate which regulates a timing generator (31) which, thus, synchronizes the frequency sweep trigger.

Abstract: A synchronizer (10) for frequency division multiple access signals (FDMA) permits synchronization on board a communications satellite without feedback to a multitude of ground-based user stations. Fourier transform processors (12, 13) sample the FDMA signal at half the FDMA baud rate and provide a series of pulses. Frequency translators (14, 15) frequency translate each pulse to frequency align across channels the content of one respective complete symbol segment to be isolated by bandpass filters (16, 17). A demodulator 18 provides a synchronized time division multiplexed output. Two channels alternately sample the FDMA signal to obtain full decoding.A synchronization processor (20) is provided to ensure that the pulses undergo appropriate frequency translations. The synchronization processor detects TDM pulse amplitudes (at 22) and compares them (at 24) to obtain a discriminate which sets a translation frequency (at 26) for each FDMA channel.

Abstract: An overlapping frequency sweep system (10) includes a complex multiplier (15) located between two reflective array compressors (RACs 13 and 21). The complex multiplier compensates for the distortions due to both RACs by modifying the phase and amplitude of the sweep at an intermediate point in its dispersion. This permits precise calibration of the individual sweeps between the time when they are in the form of pulses and when successive sweeps overlap.A pulse source (11) provides a series of pulse inputs to the first RAC (13), the series having a predetermined period between successive pulses. The first RAC introduces differential delays as a function of frequency, the maximum differential delay introduced in a given sweep being equal to or less than the period of the pulse series. The remainder of the desired dispersion is applied by the second RAC (21). A limiter (23) provides a constant amplitude function of frequency input to the complex multiplier.

Abstract: A frequency sweep system (10) operating in the radio frequency range includes a pulse source, a reflective array compresser (RAC) (13) and a complex multiplier (15). The RAC is designed to apply a time dispersion as a monotonic function of frequency to a pulse generated by the pulse source. Since RACs are difficult to manufacture precisely, the complex multiplier is included to compensate for the imperfections in the RAC. The complex multiplier is designed to multiply its analog input by a sequence of complex digital words, including a sign bit, so that the phase and amplitude of the analog signal can be calibrated as required. The sequence of digital words is determined by comparing the desired and actual phase dispersions of the frequency sweep system. The sequence so determined is stored in a read-only memory (ROM) (17). A timing generator (19) coordinates the firing of the pulse and the introduction of the sequence of digital words into the complex multiplier.

Abstract: An analog radio frequency spectrum analyzer (10) includes a calibration section (30) for compensating distortions. The spectrum analyzer includes a first reflective array compressor or "RAC" (12), a frequency sweep section (20), and a second RAC (14). Frequency domain compensations introduced at the signal input by the calibration section compensate distortions in the time domain at the output of the spectrum analyzer. This system corrects, for example, nonlinearities in the second RAC. The calibration function is determined by a network analysis of the spectrum analyzer and is specific to the RAC included. The function is stored in a ROM or other memory as a sequence of complex digital words. An address generator (36) directs the words to a complex multiplier (32) so that each input symbol period is multiplied by the sequence. Each complex digital word corresponds to an amplitude and phase modulation of the incoming signal over a fraction of a symbol period.

Abstract: An extremely fast, highly regulated and nonresistive semiconductor digital logic inverter gate which is suitable for use as a fundamental building block in an uncommitted gate array includes an input conductor, at least one output conductor, a first current source providing a fixed current of a given magnitude to the input conductor, a second current source providing a current varying exponentially with input voltage to each output conductor, and a current control circuit operating in response to current flow through the input conductor to control the magnitude of current provided by the second source of current to each of the output conductors at a magnitude greater than the first magnitude or at a nonzero magnitude substantially less than the first magnitude.