Patents by Inventor Rex K. Hales

Rex K. Hales has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8890739
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: November 18, 2014
    Assignee: Crest Semiconductors, Inc.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf Haque
  • Patent number: 8890729
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Grant
    Filed: January 26, 2013
    Date of Patent: November 18, 2014
    Assignee: Crest Semiconductors, Inc.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf A. Haque
  • Publication number: 20140152478
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Application
    Filed: January 26, 2013
    Publication date: June 5, 2014
    Applicant: CREST SEMICONDUCTORS, INC.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf A. Haque
  • Publication number: 20140152477
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 5, 2014
    Applicant: CREST SEMICONDUCTORS, INC.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf Haque
  • Patent number: 8542143
    Abstract: A pipelined Analog-to-Digital Converter (ADC) stage includes a main sampling path having a first filter in series with a first sample and hold circuit and a sub-ADC sampling path having a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC). The frequency response of the main sampling path is matched to a frequency response of the sub-ADC sampling path such that a residue signal of the pipelined ADC stage stays within range.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: September 24, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Yusuf Haque, Ryan James Kier, Rex K. Hales, Paul Talmage Watkins, Marcellus C. Harper
  • Publication number: 20130234870
    Abstract: A pipelined Analog-to-Digital Converter (ADC) stage includes a main sampling path having a first filter in series with a first sample and hold circuit and a sub-ADC sampling path having a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC). The frequency response of the main sampling path is matched to a frequency response of the sub-ADC sampling path such that a residue signal of the pipelined ADC stage stays within range.
    Type: Application
    Filed: March 6, 2012
    Publication date: September 12, 2013
    Applicant: CREST SEMICONDUCTORS, INC
    Inventors: Yusuf Haque, Ryan James Kier, Rex K. Hales, Paul Talmage Watkins, Marcellus C. Harper
  • Patent number: 8525596
    Abstract: A reference buffer amplifier within an integrated circuit includes a first output terminal connected to a first bond pad, the first bond pad being connected to a first external pin of the integrated circuit chip, the first external pin to allow an external capacitance to be connected to the output terminal. The reference buffer further includes a variable, settable resistance sub-circuit connected to a second bond pad, the second bond pad also being connected to the first external pin. The resistance sub-circuit is configured to be set to exhibit a resistance value to critically dampen a response of the reference buffer amplifier.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: September 3, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Tracy Johancsik, Rex K. Hales, Ryan James Kier, Yusuf Haque
  • Patent number: 8497790
    Abstract: A pipelined Analog-to-Digital Converter (ADC) includes circuitry to characterize capacitors associated with a Multiplying-Digital-to-Analog Converter (MDAC) of a stage of said pipelined ADC, said capacitors contributing to a gain of said pipelined ADC, circuitry to connect a subset of said capacitors not currently being characterized to reference signals of said pipelined ADC such that a residue signal of said stage stays within an input range of an instrument measuring said residue signal, circuitry to calculate said gain of said pipelined ADC using said capacitor characterizations, and an output adjusting component to digitally change an output of said pipelined ADC to compensate for said calculated gain.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: July 30, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Donald E. Lewis, Ryan James Kier, Paul Talmage Watkins, Rex K. Hales, Yusuf Haque
  • Publication number: 20130120066
    Abstract: A reference buffer amplifier within an integrated circuit includes a first output terminal connected to a first bond pad, the first bond pad being connected to a first external pin of the integrated circuit chip, the first external pin to allow an external capacitance to be connected to the output terminal. The reference buffer further includes a variable, settable resistance sub-circuit connected to a second bond pad, the second bond pad also being connected to the first external pin. The resistance sub-circuit is configured to be set to exhibit a resistance value to critically dampen a response of the reference buffer amplifier.
    Type: Application
    Filed: November 11, 2011
    Publication date: May 16, 2013
    Applicant: CREST SEMICONDUCTORS, INC
    Inventors: Tracy Johancsik, Rex K. Hales, Ryan James Kier, Yusuf Haque
  • Patent number: 8410967
    Abstract: An analog-to-digital converter includes a comparator configured to receive a first input signal and a second input signal, in which at least one of the input signals is received between two transistors, each of the transistors being in common-gate configuration. A method for comparing input signals performed by a comparator circuit includes: receiving a first input signal between a drain terminal of a first transistor of the comparator circuit and a source terminal of a second transistor of the comparator circuit; receiving a second input signal; and outputting a value based on a comparison of the first input signal and the second input signal.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: April 2, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Rex K. Hales, Paul Talmage Watkins
  • Patent number: 8242946
    Abstract: A pipelined Analog-to-Digital Converter (ADC) comprising a number of stages, at least one of the stages includes a sample and hold circuit. The sample and hold circuit includes a first output connected to an input of a sub-ADC, an output of the sub-ADC connected to an input of a Digital-to-Analog Converter (DAC), an output of the DAC connected to a node, and a second output connected to the node. The sample and hold circuit is configured to independently scale a signal produced by the first output and a signal produced by the second output.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: August 14, 2012
    Assignee: Crest Semiconductors, Inc.
    Inventors: Tracy Johancsik, Rex K. Hales
  • Publication number: 20120133539
    Abstract: An analog-to-digital converter includes a comparator configured to receive a first input signal and a second input signal, in which at least one of the input signals is received between two transistors, each of the transistors being in common-gate configuration.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Applicant: SIFLARE, INC.
    Inventors: Rex K. Hales, Paul Talmage Watkins
  • Patent number: 8026838
    Abstract: A current-mode analog-to-digital converter includes: a current input node; a current-mode sample and hold circuit configured to output a steady source of electrical current having an analog value proportional to a sampled analog value of an electrical current at the current input node; and at least one current comparator that compares the electrical current output by the current-mode sample and hold circuit to at least one reference current to produce a digital representation of the sampled analog value of the electrical current at the current input node.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: September 27, 2011
    Assignee: Siflare, Inc.
    Inventors: Rex K. Hales, Marcellus C. Harper, Tracy Johancsik, Yusuf Haque
  • Patent number: 7898452
    Abstract: This method increases accuracy of a pipelined analog-to-digital converter comprising a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). The method includes calibrating each the ADC starting from a least significant stage until all ADCs have been calibrated using a reference digital-to-analog converter, the reference digital-to-analog converter selectively outputting values at desired trip points for each the ADC; measuring an output of each the DAC using downstream stages of the pipelined analog-to-digital converter to produce output measurements; and using the output measurements to calculate an error-corrected output of the pipelined analog-to-digital converter. The trip points are adjusted by modifying a reference current input to a comparator of each the ADC.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: March 1, 2011
    Assignee: Siflare, Inc.
    Inventors: Donald E. Lewis, Rex K. Hales
  • Publication number: 20100321227
    Abstract: A current-mode analog-to-digital converter includes: a current input node; a current-mode sample and hold circuit configured to output a steady source of electrical current having an analog value proportional to a sampled analog value of an electrical current at the current input node; and at least one current comparator that compares the electrical current output by the current-mode sample and hold circuit to at least one reference current to produce a digital representation of the sampled analog value of the electrical current at the current input node.
    Type: Application
    Filed: August 27, 2010
    Publication date: December 23, 2010
    Applicant: SIFLARE INC.
    Inventors: Rex K. Hales, Marcellus C. Harper, Tracy Johancsik, Yusuf Haque
  • Publication number: 20100295714
    Abstract: A pipelined Analog-to-Digital Converter (ADC) comprising a number of stages, at least one of the stages includes a sample and hold circuit. The sample and hold circuit includes a first output connected to an input of a sub-ADC, an output of the sub-ADC connected to an input of a Digital-to-Analog Converter (DAC), an output of the DAC connected to a node, and a second output connected to the node. The sample and hold circuit is configured to independently scale a signal produced by the first output and a signal produced by the second output.
    Type: Application
    Filed: August 3, 2010
    Publication date: November 25, 2010
    Applicant: SIFLARE, INC.
    Inventors: Tracy Johancsik, Rex K. Hales
  • Patent number: 7839318
    Abstract: A pipelined analog-to-digital converter includes a plurality of stages each including a sample-and-hold circuit configured to output an analog signal having a current and a current mode analog-to-digital converter configured to compare the current of the analog signal output by the sample-and-hold circuit to current generated by a plurality of current sources and output a digital representation of the analog signal.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: November 23, 2010
    Assignee: SiFlare, Inc
    Inventors: Thomas L. Wolf, Rex K. Hales
  • Patent number: 7804436
    Abstract: A current measuring system has an electrical component configured to provide an electrical current representative of a parameter of interest at an output node; and an analog to digital converter having a current input node in electrical communication with the output node of the electrical component.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: September 28, 2010
    Assignee: SiFlare, Inc
    Inventors: Rex K. Hales, Marcellus C. Harper
  • Patent number: 7688238
    Abstract: A pipelined analog-to-digital converter includes a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). A method for increasing the accuracy of the pipelined ADC includes calibrating the ADC in each stage of the analog-to-digital converter by adjusting trip points of that ADC. Another method for increasing the accuracy of a pipelined ADC includes measuring error in an output of each the DAC; and correcting an output of the pipelined analog-to-digital converter for the measured error. These methods can be used together to further increase the accuracy of the pipelined ADC. Consequently, a pipelined analog-to-digital converter may include a look-up table containing data for correcting errors in output of each of the DACs, where trip points of the ADCs the ADCs in the stages of the pipelined converter have been calibrated to expected values.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: March 30, 2010
    Assignee: Slicex, Inc.
    Inventors: Donald E. Lewis, Rex K. Hales
  • Publication number: 20100066575
    Abstract: This method increases accuracy of a pipelined analog-to-digital converter comprising a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). The method includes calibrating each the ADC starting from a least significant stage until all ADCs have been calibrated using a reference digital-to-analog converter, the reference digital-to-analog converter selectively outputting values at desired trip points for each the ADC; measuring an output of each the DAC using downstream stages of the pipelined analog-to-digital converter to produce output measurements; and using the output measurements to calculate an error-corrected output of the pipelined analog-to-digital converter. The trip points are adjusted by modifying a reference current input to a comparator of each the ADC.
    Type: Application
    Filed: November 23, 2009
    Publication date: March 18, 2010
    Applicant: SLICEX, INC.
    Inventors: Donald E. Lewis, Rex K. Hales