Abstract: Disclosed is a heat sink for cooling an integrated circuit package. The heat sink comprises a single thin sheet of material having two oppositely facing major surfaces. These two major surfaces have a common perimeter defining a plurality of spaced-apart finger-shaped portions of the thin sheet of material that extend radially from a central portion of the sheet. The central portion is convex for attachment to the integrated circuit package; and the finger-shaped portions are formed to extend out of the plane of the central portion to become cooling fins for the central portion.

Abstract: Disclosed is an electrical conductor for use in an electro-mechanical connector of the type which holds an integrated circuit package and connects the package to an electrical system in a replaceable fashion. The electrical conductor is comprised of an elongated piece of material having a U-shaped bend to provide two legs; one of the legs also has a bend of approximately 90.degree. in a first direction at a predetermined distance from said U-shaped bend to thereafter provide a first leg portion for pushing against and making ohmic contact with a corresponding lead in said integrated circuit package; and the other leg also has a bend of approximately 90.degree. in the first direction at another predetermined distance from the U-shaped bend, and another bend of approximately 90.degree. further along its length in a direction perpendicular to the first direction to thereafter provide a second leg portion for making ohmic contact with said electrical system.

Abstract: A method and circuitry are disclosed for correcting bit errors introduced by random events in a data recirculating memory, such as a charge coupled memory device or a bubble memory. The bit errors, caused by random events such as by alpha particle bombardment or other causes, are corrected in circuitry that generates row and column parity bits corresponding to various segments of the information stored in the memory. Changes in the row and column parity bits uniquely define the location of failed bits circulating through the memory even though each failed bit has no fixed address, so that error detection circuitry thereafter may correct the error during the next or a subsequent bit recirculating cycle. The invention facilitates the use of very large memories, for example, on the order of one billion bits or more.